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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)最新文献

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Fault analysis of the multiple valued logic using spectral method 用谱法分析多值逻辑的故障
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848601
Jong O. Kim, P. Lala, Y. G. Kim, Heung-Soo Kim
{"title":"Fault analysis of the multiple valued logic using spectral method","authors":"Jong O. Kim, P. Lala, Y. G. Kim, Heung-Soo Kim","doi":"10.1109/ISMVL.2000.848601","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848601","url":null,"abstract":"A method for detecting faults in Multiple Valued Logic (MVL) is proposed. The method depends on analyzing the spectral coefficients that are transformed for the Chrestenson spectral domain. The fault detecting conditions are derived for a single input stuck-at fault, multiple input s-a-f, a s-a-f at internal lines, and Min/Max bridging fault of the MVL. Fault detection is done based on the number of coefficients affected by a fault, and hence it is independent of the technology used for construction of networks and the types of fault. This method allows detection of the fault without the test vector, and minimize the memory size for storing test vectors and response data.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access 基于多值码分多址的VLSI系统高效数据传输技术
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848654
Y. Yuminaka, Osamu Katoh, Y. Sasaki, T. Aoki, T. Higuchi
{"title":"An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access","authors":"Y. Yuminaka, Osamu Katoh, Y. Sasaki, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.2000.848654","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848654","url":null,"abstract":"This paper investigates a multiple-valued code-division multiple access (MV-CDMA) technique to achieve efficient data transmission and processing in VLSI systems. CDMA employs a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier. Orthogonal property of m-sequences enables us to multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission. With reduced interconnection. Also, randomness of m-sequences offers the high tolerance to noise interference. In the case of conventional CDMA, however, co-channel interference due to carrier phase offset error severely restricts the available number of multiplexing. In order to eliminate carrier phase offset error, we propose a new class of multiple-valued m-sequences. An application example of neural networks is discussed to demonstrate the feasibility of MV-CDMA in terms of reducing interconnections and eliminating co-channel interference.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133563792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
MDD-based synthesis of multi-valued logic networks 基于mdd的多值逻辑网络综合
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848598
R. Drechsler, M. Thornton, D. Wessels
{"title":"MDD-based synthesis of multi-valued logic networks","authors":"R. Drechsler, M. Thornton, D. Wessels","doi":"10.1109/ISMVL.2000.848598","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848598","url":null,"abstract":"A method for the synthesis of large Multi-Valued Logic Networks (MVLNs) using Multi-Valued Decision Diagrams (MDDs) is presented. The size of the resulting circuit is linear in the size of the original MDD. In contrast to previously presented approaches to circuit design using MDDs, here the nodes are not substituted by multiplexers. Instead, a small circuit is created representing the functionality of each edge in the graph. The resulting circuits have nice properties with respect to area/delay estimation and power dissipation. Experimental results are given to illustrate the efficiency of the approach.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133263344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams 用多值伪kronecker决策图表示多输出开关函数
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848613
H. M. H. Babu, Tsutomu Sasao
{"title":"Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams","authors":"H. M. H. Babu, Tsutomu Sasao","doi":"10.1109/ISMVL.2000.848613","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848613","url":null,"abstract":"In this paper, we propose a method to construct smaller multiple-valued pseudo-Kronecker decision diagrams (MVPKDDs). Our method first generates a 4-valued input 2-valued multiple-output function from a given 2-valued input 2-valued output functions. Then, it constructs a 4-valued decision diagram (4-valued DD) to represent the generated 4-valued input function. Finally, it selects a good expansion among 27 different expansions for each 4-valued node of the 4-valued DD and derive a 4-valued PKDD. We present heuristics to produce compact 4-valued PKDDs. Experimental results using benchmark functions show the efficiency of our method. From experiments, we also conjecture that, for n>1, to represent an n-bit adder (adr n), a 4-valued PKDD, a 4-valued DD (MDD), a 2-valued PKDD, and a shared binary decision diagram (SBDD) require 2n+1, 3n-1, 4n-1, and 9n-7 non-terminal nodes, respectively.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Data mining of weak functional decompositions 弱功能分解的数据挖掘
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848603
S. Jaroszewicz, D. Simovici
{"title":"Data mining of weak functional decompositions","authors":"S. Jaroszewicz, D. Simovici","doi":"10.1109/ISMVL.2000.848603","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848603","url":null,"abstract":"A weak decomposition of an incompletely specified function f is a decomposition of some completion of f. Using a graph-theoretical characterization of functions that admit such decompositions, we present a technique derived from the a priori algorithm that allows a data mining approach to identifying these decompositions.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Independence of the axioms of Boolean algebra in multiple-valued logic 多值逻辑中布尔代数公理的独立性
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848607
T. Ninomiya, M. Mukaidono
{"title":"Independence of the axioms of Boolean algebra in multiple-valued logic","authors":"T. Ninomiya, M. Mukaidono","doi":"10.1109/ISMVL.2000.848607","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848607","url":null,"abstract":"We apply the Method of Indeterminate Coefficients to examine independence of some sets of axioms of Boolean algebra and to list up some candidates of independent and complete sets of axioms of Boolean algebra. And we prove for some of these candidates that they are in fact independent and complete.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124904384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new algorithm to compute quaternary Reed-Muller expansions 计算四元Reed-Muller展开的新算法
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848614
S. Rahardja, B. Falkowski
{"title":"A new algorithm to compute quaternary Reed-Muller expansions","authors":"S. Rahardja, B. Falkowski","doi":"10.1109/ISMVL.2000.848614","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848614","url":null,"abstract":"A new algorithm to construct a full polarity matrix for n-variable quaternary Reed-Muller expansions has been introduced. The new algorithm directly utilizes the truth vector of the function to construct the polarity matrix. The computational complexity of the algorithm is analyzed and compared with other existing algorithms. It is shown that for n/spl les/6, the new algorithm is computationally more efficient than all existing algorithms. Finally the fast flow diagram which is useful for implementation of the algorithm in hardware has also been shown.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127770967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-radix parallel VLSI dividers without using quotient digit selection tables 不使用商数字选择表的高基数并行VLSI分频器
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848642
T. Aoki, Kimihiko Nakazawa, T. Higuchi
{"title":"High-radix parallel VLSI dividers without using quotient digit selection tables","authors":"T. Aoki, Kimihiko Nakazawa, T. Higuchi","doi":"10.1109/ISMVL.2000.848642","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848642","url":null,"abstract":"This paper presents the design and evaluation of high-radix parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with less hardware complexity, in comparison with the binary counterparts. This paper also presents the experimental fabrication of the radix-4 divider in 0.35 /spl mu/m CMOS technology.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130151377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Fast transforms for multiple-valued input binary output PLI logic 快速变换多值输入二进制输出PLI逻辑
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848599
B. Falkowski, S. Rahardja
{"title":"Fast transforms for multiple-valued input binary output PLI logic","authors":"B. Falkowski, S. Rahardja","doi":"10.1109/ISMVL.2000.848599","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848599","url":null,"abstract":"Fast forward and inverse transforms for multiple-valued input binary output PLI logic are derived. New matrix functions are introduced which allow feasible transformation of arbitrary q-valued input binary output functions. This allows representation of the function in the algebra of GF(2), where q/spl ges/2. The representation of MVB functions in various functional bases having always fast algorithms is the foundation for the efficient synthesis of PLI expansions of MVB functions. The computational complexity of such algorithms is essentially reduced when compared to standard matrix multiplication and inversion based methods of the earlier work in PLI logic.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129873594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage 基于dram单元的多值逻辑存储器VLSI，具有电荷添加和电荷存储功能
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848652
T. Hanyu, H. Kimura, M. Kameyama
{"title":"DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage","authors":"T. Hanyu, H. Kimura, M. Kameyama","doi":"10.1109/ISMVL.2000.848652","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848652","url":null,"abstract":"A multiple-valued logic-in-memory VLSI with fast reprogrammability is proposed to realize transfer-bottleneck-free VLSI systems. A basic component, in which a dynamic storage function and a multiple-valued threshold-literal function are merged, can be simply implemented by charge addition and charge storage with a DRAM-cell-based circuit structure. Any logic circuits with multiple-valued inputs and binary outputs can be realized by the combination of the basic components and logic-value conversion. As a typical example, a fully parallel magnitude comparator between three-valued input and stored words is designed by using the proposed logic-in-memory VLSI architecture. Its performance is superior to that of a corresponding binary implementation by using HSPICE simulation under a 0.5-/spl mu/m CMOS technology.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130950050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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