MDD-based synthesis of multi-valued logic networks

Abstract

A method for the synthesis of large Multi-Valued Logic Networks (MVLNs) using Multi-Valued Decision Diagrams (MDDs) is presented. The size of the resulting circuit is linear in the size of the original MDD. In contrast to previously presented approaches to circuit design using MDDs, here the nodes are not substituted by multiplexers. Instead, a small circuit is created representing the functionality of each edge in the graph. The resulting circuits have nice properties with respect to area/delay estimation and power dissipation. Experimental results are given to illustrate the efficiency of the approach.