{"title":"Novel resonant-tunneling multiple-threshold logic circuit based on switching sequence detection","authors":"T. Waho, K. Hattori, K. Honda","doi":"10.1109/ISMVL.2000.848638","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848638","url":null,"abstract":"We present a novel multiple-threshold circuit using resonant-tunneling diodes (RTDs). The logic operation is based on detecting a switching sequence in the RTD circuit. This scheme enables us to increase the number of threshold voltages by more than a factor of two compared with previous RTD-based MVL circuits. SPICE simulation shows that the circuit can operate at a clock frequency as high as 10 GHz. A 4-bit flash analog-to-digital converter, which uses the present circuit as a quantizer, is also discussed.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116794358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new class of fuzzy modifiers","authors":"M. D. Cock, E. Kerre","doi":"10.1109/ISMVL.2000.848609","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848609","url":null,"abstract":"In this paper we introduce a new class of fuzzy modifiers based on fuzzy relations. We apply them in the framework of linguistic variables, which plays a key role in fuzzy control. More precisely we will use the new class of fuzzy modifiers for the representation of weakening, intensifying and ordering-based linguistic modifiers. Furthermore we will also show how these fuzzy modifiers can be applied in image processing.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125899398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic synthesis of controllers for B-ternary asynchronous systems","authors":"Y. Nagata, D. M. Miller, M. Mukaidono","doi":"10.1109/ISMVL.2000.848650","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848650","url":null,"abstract":"Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case. In this paper, a logic synthesis approach for designing the controller for a B-ternary data-path we have presented earlier is discussed. To control the B-ternary data-path asynchronously, external-binary, internal-ternary signaling is required. We derive an asynchronous state transition graph from the signal transition graph of the controller and then synthesize a hazard-free asynchronous implementation of the controller as a two-level combinational circuit together with a ternary-in binary-out C-element.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129039950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Propagation algorithm of behavior probability in power estimation based on multiple-valued logic","authors":"Xunwei Wu, Massoud Pedram","doi":"10.1109/ISMVL.2000.848657","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848657","url":null,"abstract":"This paper analyses the propagation operations of signal's multiple-valued behavior while passing through the basic gates. Based on it the propagation algorithm of behavior probability is proposed. In comparison with the propagation algorithm of signal probability this algorithm have advantages that the calculation is direct one and the glitches resulted from race hazard can be taken into account, whereby the estimation accuracy of power dissipation can be improved.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124748751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite-valued approximations of product logic","authors":"S. Aguzzoli, B. Gerla","doi":"10.1109/ISMVL.2000.848617","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848617","url":null,"abstract":"In this paper we shall propose a method for the reduction of the problem of decidability in propositional infinite-valued Product Logic to suitably determined finite-valued approximating logics. In order to do so, functions associated with formulas of product logic are defined and their properties are exploited.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121598948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Hata, Syoji Kobashi, N. Kamiura, Yuri T. Kitamura, T. Yanagida
{"title":"On an architecture of medical image registration system based on multiple-valued logic","authors":"Y. Hata, Syoji Kobashi, N. Kamiura, Yuri T. Kitamura, T. Yanagida","doi":"10.1109/ISMVL.2000.848631","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848631","url":null,"abstract":"This paper proposes an architecture of a registration system for medical images. Image registration is the process of determining correspondence between all points in two images of the same scene, and is now widely used to medical images. In medical imaging, segmentation, registration and interpolation play primary roles. In those registration is the most time consuming task because we must compare all voxel data and then evaluate the matching degree many times. Quantitative evaluation criterion of matching degree with multiple-valued coding of the image feature is proposed, and an architecture to save the processing time of the data comparison is described. Finally, as a practical application, we describe the summary of a registration of human brain MR volume data to diagnose brain disease.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131536989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The 2-SAT problem of regular signed CNF formulas","authors":"Bernhard Beckert, Reiner Hähnle, F. Manyà","doi":"10.1109/ISMVL.2000.848640","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848640","url":null,"abstract":"Signed conjunctive normal form (signed CNF) is a classical conjunctive clause form using a generalized notion of literal, called signed atom. A signed atom is an expression of the form S:p, where p is a classical atom and S, its sign, is a subset of a domain N. The informal meaning is \"p rakes one of the values in S \" Applications for deduction in signed logics derive from those of annotated logic programming (e.g., mediated deductive databases), constraint programming (e.g., scheduling), and many-valued logics (e.g., natural language processing). The central role of signed CNF justifies a detailed study of its subclasses, including algorithms for and complexities of associated SAT problems. Continuing previous work (1999), in this paper we present new results on the complexity of the signed 2-SAT problem; i.e., the case in which all clauses of a signed CNF formula have at most two literals.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133588802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel /spl Pi/-type resistor network in D/A converter based on multiple-valued logic","authors":"Xunwei Wu, Xuanchang Zhou","doi":"10.1109/ISMVL.2000.848624","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848624","url":null,"abstract":"The paper analyses the mathematical expression of digital-to-analog conversion and explains the physical realization of a binary DAC by means of dividing current, whereby the resistor network of the quaternary DAC is proposed. By using quaternary signal decode, a novel /spl Pi/-type resistor network is derived. Compared with the conventional T-type resistor network, a quarter of resistors in this network can be saved and the precision is ensured.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structures with many-valued information and their relational proof theory","authors":"I. Düntsch, W. MacCaull, E. Orlowska","doi":"10.1109/ISMVL.2000.848635","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848635","url":null,"abstract":"We present a uniform relational framework for developing proof systems for theories of manyvaluedness that may have the form of a logical system, of a class of algebra or of an information system. We outline a construction of proof systems for SH/sub n/ logics, mv-algebra and many-valued information systems.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123548358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gray scale image compression based on multiple-valued input binary functions, Walsh and Reed-Muller spectra","authors":"B. Falkowski, L. Lim","doi":"10.1109/ISMVL.2000.848632","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848632","url":null,"abstract":"A new method for the lossless compression of gray scale images has been proposed. Coding of intensities is first applied to make the data more amenable for compression. A prediction process is performed followed by the mapping of prediction residuals. The prediction residuals are then split into bit planes to which the compression technique is applied. These bit planes can be coded as uncompressed, expressed as minterms or compressed using a variable block-size segmentation and coding. A dictionary of patterns is formed from simple multiple-valued input binary functions, basic Walsh, triangular Reed-Muller weights and some frequently occurring patterns. Other compression methods used in our scheme include minterm coding, coordinate data coding, Generalized k-Variable Mixed-Polarity Reed-Muller expansion and the reference row technique. The proposed scheme has been implemented in the C language and compared with other stare-of-the-art techniques.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}