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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)最新文献

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Lower bound sifting for MDDs mdd的下界筛选
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848619
D. Jankovic, Wolfgang Günther, R. Drechsler
{"title":"Lower bound sifting for MDDs","authors":"D. Jankovic, Wolfgang Günther, R. Drechsler","doi":"10.1109/ISMVL.2000.848619","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848619","url":null,"abstract":"Decision Diagrams (DDs) are a data structure for the representation and manipulation of discrete logic functions often applied in VLSI CAD. Common DDs to represent Boolean functions are Binary Decision Diagrams (BDDs). Multiple-valued logic functions can be represented by multiple-valued Decision Diagrams (MDDs). The effiency of a DD representation strongly depends on the variable ordering; the size may vary from linear to exponential. Finding a good ordering is an NP-hard problem that has received considerable attention resulting in many minimization methods. Sifting is the most popular heuristic for dynamic DD minimization. In this paper we give lower bounds for sifting of MDDs. Based on them, both lower bound sifting for MDD minimization and lower bound group sifting for BDD minimization are proposed. By the computation of good lower bounds large parts of the search space can be pruned resulting in very fast computations. This is demonstrated by experimental results.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129983765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Chaining techniques for automated theorem proving in many-valued logics 多值逻辑中自动定理证明的链接技术
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848641
H. Ganzinger, Viorica Sofronie-Stokkermans
{"title":"Chaining techniques for automated theorem proving in many-valued logics","authors":"H. Ganzinger, Viorica Sofronie-Stokkermans","doi":"10.1109/ISMVL.2000.848641","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848641","url":null,"abstract":"We apply chaining techniques to automated theorem proving in many-valued logics. In particular, we show that superposition specializes to a refined version of the many-valued resolution rules introduced by Baaz and Fermuller, and that ordered chaining can be specialized to a refutationally complete inference system for regular clauses.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121368766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Hardware implementation of "Supplementary symmetrical logic circuit structure" concepts 硬件实现了“补充对称逻辑电路结构”的概念
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848645
D. Olson, K. Current
{"title":"Hardware implementation of \"Supplementary symmetrical logic circuit structure\" concepts","authors":"D. Olson, K. Current","doi":"10.1109/ISMVL.2000.848645","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848645","url":null,"abstract":"A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels 采用多输入信号电平的低功率双轨多值电流模式逻辑电路
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848647
T. Hanyu, T. Ike, M. Kameyama
{"title":"Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels","authors":"T. Hanyu, T. Ike, M. Kameyama","doi":"10.1109/ISMVL.2000.848647","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848647","url":null,"abstract":"A new high-speed and low-power threshold detector is proposed to realize high-performance arithmetic VLSI systems. In a conventional threshold detector with a single supply voltage, the input signal swing of a differential-pair circuit (DPC) is too large, which causes large power dissipation together with a long switching delay. The use of two kinds of supply voltages makes the input signal swing of the DPC small, which results in a lower power dissipation together with a higher switching speed. As a typical example of the proposed multiple-valued current-mode (MVCM) logic circuit, a radix-2 signed-digit full adder is designed by using a 0.35 /spl mu/m CMOS technology. Its performance is superior to that of a corresponding MVCM logic circuit with a single supply voltage under the same transistor counts.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126806881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Properties of independent components of self-motion optical flow 自运动光流独立分量的性质
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848643
M. Jabri, Ki-Young Park, Soo-Young Lee, T. Sejnowski
{"title":"Properties of independent components of self-motion optical flow","authors":"M. Jabri, Ki-Young Park, Soo-Young Lee, T. Sejnowski","doi":"10.1109/ISMVL.2000.848643","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848643","url":null,"abstract":"In this paper we describe the properties of independent components of optical flow of moving objects. Video sequences of objects seen by an observer moving at various angles, directions and distances are used to produce optical flow maps. These maps are then, recessed using independent component analysis, which yields filters that resemble the receptive fields of dorsal medial superior temporal cells of the primate brain. Contraction, expansion, rotation and translation receptive fields have been identified. Our results support Barlow's sensory coding theory and are in-line with other work on independent components of image and video intensities.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122193199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Implementation of multiple-output functions using PQMDDs 使用pqmdd实现多输出功能
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848620
Y. Iguchi, Tsutomu Sasao, M. Matsuura
{"title":"Implementation of multiple-output functions using PQMDDs","authors":"Y. Iguchi, Tsutomu Sasao, M. Matsuura","doi":"10.1109/ISMVL.2000.848620","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848620","url":null,"abstract":"A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (shared reduced ordered Binary Decision Diagrams). In this paper, we propose PQMDD (Paged Quasi-reduced ordered Multi-valued Decision Diagram) as a new data structure. A function is represented by a PQMDD, and stored in memory. Dedicated control circuits traverse the PQMDD in parallel. We represent multiple-output function for benchmark functions by SBDDs and PQMDDs and compare the size of memory and computation time.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop 基于多结表面隧道晶体管的新型多值t型栅极的演示及其在三值数据触发器中的应用
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848636
T. Uemura, T. Baba
{"title":"Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop","authors":"T. Uemura, T. Baba","doi":"10.1109/ISMVL.2000.848636","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848636","url":null,"abstract":"A novel T-gate consisting of multi-junction surface tunnel transistors (MJ-STTs) and hetero-junction FETs (HJFETs) were proposed and its operation was successfully confirmed by both simulation and experiment. The number of the devices required for their-gate can be drastically reduced due to a high functionality of the MJ-STT. Only three MJ-STTs and three HJFETs were required to fabricate the three-valued T-gate, whose number is less than one half of that of the conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic function. Furthermore, a multiple-valued data flip-flop (D-FF) circuit could be realized by only one T-gate.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124326129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fibonacci decision diagrams and spectral Fibonacci decision diagrams 斐波那契决策图和谱斐波那契决策图
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848621
R. Stankovic, M. Stankovic, J. Astola, K. Egiazarian
{"title":"Fibonacci decision diagrams and spectral Fibonacci decision diagrams","authors":"R. Stankovic, M. Stankovic, J. Astola, K. Egiazarian","doi":"10.1109/ISMVL.2000.848621","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848621","url":null,"abstract":"The authors define the Fibonacci decision diagrams (FibDDs) permitting representation of functions defined in a number of points different from N=2/sup n/ by decision diagrams consisting of nodes with two outgoing edges. We show the relationships between the FibDDs and the contracted Fibonacci codes. Then, we define the Spectral Fibonacci DDs (FibSTDDs) in terms of the generalized Fibonacci transforms. This broad family of transforms provides a corresponding family of FibSTDDs. These DDs allow compact representations of functions with simple Fibonacci spectra. Such representations may be useful in various tasks of signal processing, including image processing and systems design, where the generalized Fibonacci transforms have been efficiently used.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integration of information in four-valued logics under non-uniform assumptions 非均匀假设下四值逻辑中的信息集成
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848618
Yann Loyer, N. Spyratos, D. Stamate
{"title":"Integration of information in four-valued logics under non-uniform assumptions","authors":"Yann Loyer, N. Spyratos, D. Stamate","doi":"10.1109/ISMVL.2000.848618","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848618","url":null,"abstract":"We study the problem of integrating information coming from different sources in a distributed environment. We assume a central server that collects facts from sources and tries to combine them using a set of logical rules, i.e. a logic program. We provide a formal framework for the integration of information in such a setting, under non-uniform assumptions on the missing information.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Controllability/observability measures for multiple-valued test generation based on D-algorithm 基于d算法的多值测试生成的可控性/可观察性度量
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848627
N. Kamiura, Y. Hata, N. Matsui
{"title":"Controllability/observability measures for multiple-valued test generation based on D-algorithm","authors":"N. Kamiura, Y. Hata, N. Matsui","doi":"10.1109/ISMVL.2000.848627","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848627","url":null,"abstract":"In this paper we propose controllability and observability measures to guide the D-algorithm for multiple-valued logic circuits. The former is determined in one forward traversal of the circuit, and used in determining the line where the consistency operation should proceed. The latter is determined in one backward traversal, and used in executing the D-drive at the fanout point. Our measures are computed by simple recursive formulas, and the time required for computing them is relatively short. The experimental results show that our measures are helpful in reducing the number of times for backtracking.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116104296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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