硬件实现了“补充对称逻辑电路结构”的概念

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI:10.1109/ISMVL.2000.848645

D. Olson, K. Current

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引用次数: 11

摘要

采用补充对称逻辑电路结构(SUS-LOC)概念，在标准的1.2微米CMOS工艺中制作了测试芯片。测试芯片展示了几种三元逻辑功能以及SUS-LOC结构的灵活性。对芯片的逻辑功能和开关性能进行了仿真和实验验证。给出了仿真和实验结果并进行了讨论。

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Hardware implementation of "Supplementary symmetrical logic circuit structure" concepts

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed.

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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

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