Hardware implementation of "Supplementary symmetrical logic circuit structure" concepts

Abstract

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed.