Logic synthesis of controllers for B-ternary asynchronous systems

Abstract

Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case. In this paper, a logic synthesis approach for designing the controller for a B-ternary data-path we have presented earlier is discussed. To control the B-ternary data-path asynchronously, external-binary, internal-ternary signaling is required. We derive an asynchronous state transition graph from the signal transition graph of the controller and then synthesize a hazard-free asynchronous implementation of the controller as a two-level combinational circuit together with a ternary-in binary-out C-element.