Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)最新文献_第5页

Experiments on FPRM expressions for partially symmetric logic functions 部分对称逻辑函数的FPRM表达式实验

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848612

S. Yanushkevich, J. T. Butler, G. Dueck, V. Shmerko

引用次数: 9

Probabilistic verification of multiple-valued functions 多值函数的概率验证

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848659

E. Dubrova, Harald Sack

引用次数: 18

Implementation of multiple-valued multiplier on GF(3/sup m/) using current mode CMOS 利用电流模CMOS在GF(3/sup m/)上实现多值乘法器

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848623

Hyeon-Kyeong Seong, J. Choi, Boo Sik Shin, Heung-Soo Kim

引用次数: 1

Multi-valued logic pass gate network using neuron-MOS transistors 基于神经元- mos晶体管的多值逻辑通栅极网络

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848594

Jing Shen, M. Inaba, K. Tanno, O. Ishizuka

{"title":"Multi-valued logic pass gate network using neuron-MOS transistors","authors":"Jing Shen, M. Inaba, K. Tanno, O. Ishizuka","doi":"10.1109/ISMVL.2000.848594","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848594","url":null,"abstract":"A multi-valued logic (MVL) pass gate is an important element to configure multi-valued logic networks. Different from binary pass gates, multiple logical levels are required to be discriminated in MVL pass gates. In this paper, according to the feature of the threshold operation of a neuron MOS transistor (VMOS), two types of MVL pass gates using /spl nu/MOS are presented. One type, a CMOS MVL pass gate with VMOS down literal circuit, is composed of a CMOS pass gate and a VMOS threshold gate (/spl nu/MOS down literal circuit (DLC)). The discrimination between different MVL signals is realized by the threshold gate. Another type, a /spl nu/MOS hybrid pass gate, consists of a /spl nu/MOS transistor, a MOS transistor and a binary inverter. The VMOS transistor as used as a pass transistor, and the threshold discrimination is directly implemented by the VMOS pass gate. The latter is more compact than the former. The number of transistors and the layout area of the MVL network can be reduced by using /spl nu/MOS hybrid pass gates, while the bias setting is easier by using CMOS MVL pass gates. The common advantages of the proposed pass gates are low fabrication cost and possibility to build reconfigurable networks.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127823524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Some properties of discrete interval truth valued logic 离散区间真值逻辑的若干性质

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848606

N. Takagi, K. Nakashima

{"title":"Some properties of discrete interval truth valued logic","authors":"N. Takagi, K. Nakashima","doi":"10.1109/ISMVL.2000.848606","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848606","url":null,"abstract":"This paper focus on functions defined on a special subset of the power set of {0, 1, ..., r-1} (the elements in the subset will be called discrete interval truth values because they act precisely as intervals) and operations on. The truth values. The operations discussed in this paper will be called regular because they can be seen as an extension of the regularity which was introduced by Kleene in his ternary logic. M. Mukaidono investigated some properties of ternary functions which can be represented by the regular operations. He called such ternary functions \"regular ternary logic functions\". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states and/or initial stated in binary logic circuits that Boolean functions cannot cope with. They are also applicable to studied of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions to functions on the discrete interval truth values. Section 2 will give some of the basic definitions of discrete interval truth valued logic, and show dome of its mathematical properties. In Section 3 we will give logic formulas which represent minimum and maximum information loss functions.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125054944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Multi-valued sub-function encoding in functional decomposition based on information relationships measures 基于信息关系测度的功能分解中的多值子函数编码

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848604

A. Chojnacki, L. Józwiak

{"title":"Multi-valued sub-function encoding in functional decomposition based on information relationships measures","authors":"A. Chojnacki, L. Józwiak","doi":"10.1109/ISMVL.2000.848604","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848604","url":null,"abstract":"Functional decomposition is becoming more and more popular, because it is more general than all other known logic synthesis approaches and it seems to be the most effective approach for LUT-based FPGAs, (C)PLDs and complex CMOS-gates. The multi-level functional decomposition can be seen as a recursive splitting of a given function, into two sub-functions: the predecessor (bound-set) function and successor function, initially, the bound set function is a multi-valued (symbolic) function, where a certain value (symbol) is assigned to each particular input-cube compatibility class of the function being decomposed. To be implemented with binary logic, the multi-valued bound-set function must be expressed as a set of binary functions. This transformation is called the multi-valued sub-function encoding. It can be performed by the binary code assignment to each particular input-cube compatibility class. It determines the resulting binary predecessor and successor sub-functions and therefore influences the quality of the resulting circuit to a high degree. In this paper, a new method of the multi-valued sub-function encoding is presented. The method is based on the information relationship measures. Experimental results from the prototype CAD-tool that implements the method demonstrate that it is able to efficiently construct extremely effective circuits for symmetric functions. Results for asymmetric functions are also very good.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A multilevel-cell 32 Mb flash memory 多单元32mb闪存

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848644

Mark E. Bauer, R. Alexis, Gregory E. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, Jahanshir J. Javanifard, Marcus E. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, K. Wojciechowski

引用次数: 78

On the number of dependent variables for incompletely specified multiple-valued functions 不完全指定多值函数的因变量数

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848605

Tsutomu Sasao

引用次数: 29

Computation of spectral information from logic netlists 逻辑网表谱信息的计算

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848600

R. Drechsler, M. Thornton

引用次数: 5

A four-valued logic B(4) of E(9) for modeling human communication E(9)的四值逻辑B(4)，用于模拟人类交流

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848633

D. Rine, R. Alnakari

引用次数: 0