Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)最新文献_第6页

Fuzzy decision diagrams for the representation, analysis and optimization of rule bases 模糊决策图用于规则库的表示、分析和优化

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848610

Karsten Strehl, C. Moraga, Karl-Heinz Temme, R. Stankovic

引用次数: 9

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices 基于负差分电阻器件的多值逻辑符号数字加法器的标准CMOS实现

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848639

Alejandro F. González, M. Bhattacharya, S. Kulkarni, P. Mazumder

引用次数: 8

On algebraic foundations of information granulation III. Investigating the HATA-MUKAIDONO approach 信息粒化的代数基础3。研究HATA-MUKAIDONO方法

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848611

H. Thiele

引用次数: 5

Neural networks: binary monotonic and multiple-valued 神经网络:二元单调与多值

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848602

J. Zurada

引用次数: 6

The synthesis of multiple-valued logic circuits using local-excitation-type neuron models 用局部激励型神经元模型合成多值逻辑电路

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848595

M. Matsumoto, Y. Ueda, Isami Nomoto

引用次数: 1

Information theoretic approach to minimization of polynomial expressions over GF(4) GF(4)上多项式表达式最小化的信息论方法

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848630

S. Yanushkevich, D. Popel, V. Shmerko, V. Cheushev, R. Stankovic

引用次数: 10

On Urquhart's C logic 关于厄克特的C逻辑

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848608

A. Ciabattoni

引用次数: 8

An evolutionary computing approach to multilevel logic synthesis using various logic operations 采用进化计算方法实现多种逻辑运算的多级逻辑综合

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848629

Takahiro Hozumi, O. Kakusho, K. Yamato

引用次数: 4

Design of a quaternary latch circuit using a binary CMOS RS latch 基于二进制CMOS RS锁存器的四元锁存电路设计

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848646

K. Current

引用次数: 6

Dynamic re-encoding during MDD minimization 在MDD最小化期间动态重新编码

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848626

Frank Schmiedle, Wolfgang Günther, R. Drechsler

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引用次数: 10