Design of a quaternary latch circuit using a binary CMOS RS latch

Abstract

A new voltage-mode quaternary CMOS static latch circuit is presented that is built around a binary standard CMOS logic clocked RS latch circuit. Only devices available in a standard digital CMOS fabrication technology-enhancement-mode NMOS and PMOS transistors with single threshold voltage values-are used. No depletion-mode devices or special transistor threshold voltages are required. Its operation is experimentally verified. Typical and worst-case on-chip setup and hold times are simulated to be approximately 2.8 ns and 6.8 ns, respectively.