利用电流模CMOS在GF(3/sup m/)上实现多值乘法器

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI:10.1109/ISMVL.2000.848623

Hyeon-Kyeong Seong, J. Choi, Boo Sik Shin, Heung-Soo Kim

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引用次数: 1

摘要

给出了有限域GF(3/sup m/)上两个多项式的乘法算法。基于GF(3/sup 3/)的串行输入/并行输出模块结构的3值乘法器将在所提出的乘法算法上执行，并由电流模CMOS实现。电流模CMOS 3值乘法器由两个GF(3)乘法器和两个GF(3)加法器实现。在标准CMOS器件参数为2.0 /spl mu/m、单位电流为20 /spl mu/A、电源为3.3 V V/sub的情况下，采用Pspice仿真对所提电路的性能进行了评估。

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Implementation of multiple-valued multiplier on GF(3/sup m/) using current mode CMOS

The multiplication algorithm of two polynomials on finite fields GF(3/sup m/) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(3/sup 3/) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 /spl mu/m standard CMOS device parameters, 20 /spl mu/A unit current level and 3.3 V V/sub DD/ voltage supply.

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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

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