{"title":"Flexible electronics - opportunities and challenges","authors":"M. Deen","doi":"10.1109/EDSSC.2013.6628198","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628198","url":null,"abstract":"The use of organic/polymeric materials to create thin film transistors on flexible substrates has advanced significantly in the past few decades. These advances are stimulated by the promise of low-cost, lighter and more robust devices and systems for applications that include large area electronics and displays, sensors and wearable systems. However, there are still many challenges to be solved before flexible electronics can realize its potential. These challenges include hysteresis and contacts effects, accurate static/dynamic compact models, and improved stability, reliability, and lifetime.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"522 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122226815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chang Qi, Xiaojun Xia, Xinzhi Shi, Ye Shuangli, Jinguang Jiang
{"title":"Circuit-level thermal model of intermediate infrared quantum cascade lasers","authors":"Chang Qi, Xiaojun Xia, Xinzhi Shi, Ye Shuangli, Jinguang Jiang","doi":"10.1109/EDSSC.2013.6628098","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628098","url":null,"abstract":"An equivalent circuit thermal model is established based on quantum cascade laser(QCL) two-level rate equation by analyzing the gain characteristic depend on the temperature in active region. The model enables the analysis of the thermal characteristics of intermediate infrared QCL using general circuit analysis software such as PSPICE. The simulation results are in agreement with reported theoretical and experimental data. That proves the practicality and accuracy of the model.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130496791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A UHF RFID reader baseband for multi-protocol with universal transmitter","authors":"Shaoxun Li, Chun Zhang, Yingying Wang, Qi Peng","doi":"10.1109/EDSSC.2013.6628220","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628220","url":null,"abstract":"In this paper, a UHF RFID reader baseband for multi-protocol with universal transmitter is present. A universal transmitter is proposed that can support all of the coding method of UHF RFID, except that a MCU of DW8051core and some supported module are included in the chip. It provides flexible choice for users to select coding method and data rate by set the related control registers. The UHF RFID Reader IC is fabricated in 0.18μm CMOS technology. The area of digital part on the right of IC is 4.4mm2. EDA tool Synopsys PrimeTime PX has been exploited for power consumption estimation with post-layout netlist, which shows that the digital baseband consumes an average power of 4.9μW (1.8V) over a succession of receiving a sequence of response. The power will rise up to 220μW (1.8V), when containing the memory part.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128185758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Bahubalindruni, Vítor M. Grade Tavares, P. Guedes de Oliveira, P. Barquinha, R. Martins, E. Fortunato
{"title":"High-gain amplifier with n-type transistors","authors":"P. Bahubalindruni, Vítor M. Grade Tavares, P. Guedes de Oliveira, P. Barquinha, R. Martins, E. Fortunato","doi":"10.1109/EDSSC.2013.6628203","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628203","url":null,"abstract":"A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 μm CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134218831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Burghartz, E. Angelopoulos, W. Appel, S. Endler, S. Ferwana, C. Harendt, M. Hassan, H. Rempp, H. Richter, M. Zimmermann
{"title":"Ultra-thin chips for flexible electronics","authors":"J. Burghartz, E. Angelopoulos, W. Appel, S. Endler, S. Ferwana, C. Harendt, M. Hassan, H. Rempp, H. Richter, M. Zimmermann","doi":"10.1109/EDSSC.2013.6628168","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628168","url":null,"abstract":"Various aspects of ultra-thin chip technology for flexible electronics based on Chipfilm™ technology are presented and discussed, including ultra-thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 116-dB CMOS op amp with repetitive gain boosting and subthreshold operation","authors":"Shi Bu, K. Leung","doi":"10.1109/EDSSC.2013.6628056","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628056","url":null,"abstract":"This work proposes a simple high-gain single-stage op amp design that operates at low power (~100 μW) and low voltage (±1 V) without severely sacrificing unity gain frequency and slew rate. Simulation results that demonstrate the performance of this design are also presented.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"127 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113991725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of microhelix inductors with focused ion beam","authors":"Z. Q. Wang, Y. Mao, L. R. Zhao, W. Wu, J. Xu","doi":"10.1109/EDSSC.2013.6628070","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628070","url":null,"abstract":"This paper describes a microhelix inductor structure fabricated with focused ion beam(FIB) stress introducing technology(SIT). With the decrease of the implantation does, the pitch and the diameter of the microhelix inductors decreases, which will also affect the performance of the microinductors. Microhelix inductors with different scales are fabricated from 120 nm thick, 2 um wide, 41um long aluminum microbeams, which are built on SOI substrate. The solenoid microinductor is fabricated with implantation does 2.83×1017cm-2. With different scales of microbeams and fabrication does, we get a microsolenoid inductor with pitch 6 um, diameter 2.3 um. So under the control of different FIB condition, we can get the desired microhelix inductor with needed pitch, diameter and turn number. The fabrication process is controllable and repeatable. We get the S parameters of the microhelix with the help of Agilent network analyzer from 100 MHz to 40 GHz at an interval of 50 MHz, after open structure and through structure deembedding process, the calculated inductance is as small as 10-4 nH, Quality factor arises from 0.02 to 0.55 when the frequency arises from 100 MHZ to 40GHZ respectively.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. V. Vasantha Kumar, M. Manjunatha, V. Suresh, Shao-Ming Yang, G. Sheu, P. A. Chen
{"title":"Effects of antimony and arsenic ion implantation on high performance of ultra high voltage device","authors":"V. V. Vasantha Kumar, M. Manjunatha, V. Suresh, Shao-Ming Yang, G. Sheu, P. A. Chen","doi":"10.1109/EDSSC.2013.6628068","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628068","url":null,"abstract":"This paper presents a low cost innovative dual channel engineering to simulate the effects of arsenic and antimony implantation over breakdown voltage and on state resistance of an Ultra High Voltage (UHV) device. There are many devices in market with multiple conduction paths, but all these devices use high energy implants. But we have used a low cost and low energy implant over P-top to form an extra conduction path. Optimizations are done to obtain high breakdown voltage and lower Ron by varying the P-top and Ntop over P-top. We demonstrate interface charge analysis for both Antimony and Arsenic implantation over P-top and also we investigate the effect of N-top implantation before and after NDrift diffusion on breakdown voltage.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of fluorine dose and implant energy to the NBTI upon p+ implant sequence","authors":"Siti Zubaidah Md Saad, T. C. Lik, S. H. Herman","doi":"10.1109/EDSSC.2013.6628076","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628076","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is one of the major issues related to p-channel metal-oxide-semiconductor (PMOS) reliability that has been discussed for more than 40 years. In this paper, we discussed the effect of fluorine (F) co-implant to the NBTI improvement, capacitance and silicon oxide (SiO2) thickness in term of F concentration, implant energy and also implant sequence at p+-region. Results suggest that, besides F dose and implant energy that is known to contribute to NBTI behaviors; implant sequence also plays a role in NBTI degradation.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ying Zhu, Ye Yun, Yu Cao, Jin He, Aixi Zhang, Hongyu He, Hao Wang, Chenyue Ma, Yue Hu, M. Chan, Xiaoan Zhu
{"title":"Numerical study on effects of random dopant fluctuation in double gate tunneling FET","authors":"Ying Zhu, Ye Yun, Yu Cao, Jin He, Aixi Zhang, Hongyu He, Hao Wang, Chenyue Ma, Yue Hu, M. Chan, Xiaoan Zhu","doi":"10.1109/EDSSC.2013.6628040","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628040","url":null,"abstract":"Impacts of random dopant fluctuations (RDFs) on the performance of an optimized double-gate (DG) tunneling FET (TFET) are studied using 3-D device simulations. The sensitivity of the TFET performance with a high-k gate dielectric to RDF is explored in this paper. Sano's approach is used to generate random doping profiles for statistical device simulation. It is found that TFET suffers from dramatic shift and fluctuations in electrical parameters (Vth, gm and SS for instance) due to RDF, thus emerging a further impact on circuit performance.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116277334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}