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IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.最新文献

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High performance AlGaN/AlN/GaN HEMTs grown on 100-mm-diameter epitaxial AlN/sapphire templates by MOVPE 利用MOVPE在直径100 mm的外延AlN/蓝宝石模板上生长高性能AlGaN/AlN/GaN hemt
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-12-01 DOI: 10.1109/CSICS.2004.1392534
M. Miyoshi, A. Imanish, H. Ishikawa, T. Egawa, K. Asai, M. Mouri, T. Shibata, M. Tanaka, O. Oda
{"title":"High performance AlGaN/AlN/GaN HEMTs grown on 100-mm-diameter epitaxial AlN/sapphire templates by MOVPE","authors":"M. Miyoshi, A. Imanish, H. Ishikawa, T. Egawa, K. Asai, M. Mouri, T. Shibata, M. Tanaka, O. Oda","doi":"10.1109/CSICS.2004.1392534","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392534","url":null,"abstract":"A/sub 0.26/Ga/sub 0.74/N/AlN/GaN heterostructures with 1-nm-thick AlN interfacial layers were grown on 100-mm-diameter epitaxial AlN/sapphire templates and sapphire substrates by metalorganic vapor phase epitaxy (MOVPE). Very high Hall mobilities of approximately 2100 cm/sup 2//Vs at room temperature and approximately 25000 cm/sup 2//Vs at 15 K with a 2DEG density of approximately 1/spl times/ 10/sup 13//cm/sup 2/ were uniformly obtained for AlGaN/ AlN/GaN heterostructures on 100-mm-diameter epitaxial AIN/ sapphire templates. High-electron-mobility transistors (HEMTs) were successfully fabricated on the AlGaN/AlN/GaN film on the epitaxial AIN/sapphire template. The fabricated devices exhibited good pinch-off characteristics and a very high intrinsic transconductance of 496 mS/mm.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122248555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SiGe BiCMOS 65-GHz BPSK transmitter and 30 to 122 GHz LC-varactor VCOs with up to 21% tuning range SiGe BiCMOS 65 GHz BPSK发射机和30至122 GHz lc变容vco，调谐范围高达21%
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392529
C. Lee, T. Yao, A. Mangan, K. Yau, M. A. Copeland, S. Voinigescu
{"title":"SiGe BiCMOS 65-GHz BPSK transmitter and 30 to 122 GHz LC-varactor VCOs with up to 21% tuning range","authors":"C. Lee, T. Yao, A. Mangan, K. Yau, M. A. Copeland, S. Voinigescu","doi":"10.1109/CSICS.2004.1392529","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392529","url":null,"abstract":"This work presents a systematic study of millimetre-wave, low-noise, widely-tuneable differential Colpitts VCOs. A design methodology was developed and validated experimentally over thirteen different varactor-tuned (VCO) and fixed-frequency L-C oscillators spanning the 30-GHz to 122-GHz frequency range. All circuits employ accumulation-mode n-MOS varactors, and multi-turn on-chip inductors. The 35-GHz and 60-GHz oscillators achieve phase noise of -112.7 dBc and -104 dBc/Hz, respectively at 1-MHz offset and deliver +4 dBm differential output power while a push-push implementation demonstrates 15-GHz (21%) tuning range from 63.5 GHz to 78.5 GHz. A directly-modulated, 65-GHz binary phase shift keying (BPSK) transmitter is also implemented.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"47 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Enhancement and depletion-mode pHEMT using 6 inch GaAs cost-effective production process 增强和耗尽模式pHEMT采用6英寸GaAs具有成本效益的生产工艺
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392506
Y. Hsieh, T. Hwang, T. Yeh, C. Yuan, C.J. Chen, P. Yeh, J.H. Hwang, C.-H. Chen, C. Wu
{"title":"Enhancement and depletion-mode pHEMT using 6 inch GaAs cost-effective production process","authors":"Y. Hsieh, T. Hwang, T. Yeh, C. Yuan, C.J. Chen, P. Yeh, J.H. Hwang, C.-H. Chen, C. Wu","doi":"10.1109/CSICS.2004.1392506","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392506","url":null,"abstract":"A cost effective enhancement/depletion mode pHEMT MMIC process on 6-inch GaAs wafer is demonstrated by using 0.5/spl mu/m gate-length optical stepper pHEMT technology. E-mode and D-mode gates are deposited simultaneously in this process simplification. The E-mode pHEMT exhibits a pinch-off voltage of +0.22V (defined at 0.1mA/mm), and a maximum extrinsic transconductance of 400mS/mm at room temperature. The off-state current of E-mode device is typically 0.15/spl mu/A/mm at V/sub gs/=0V and V/sub ds/=3V. This current is extreme low and is suitable for high density digital circuits with minimized power consumption. On the other hand, a pinch-off voltage of -0.75V and a transconductance of 370mS/mm has been measured for D-mode pHEMT. Due to excellent DC/RF characteristics and good uniformity of E/D pHEMTs from optimized optical gate lithography and front-side process, the D-mode switch and E-mode digital control circuit constitute a monolithic solution to RF control circuits in WLAN and cell phone applications.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124406066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design and development of compact CDMA/WCDMA power amplifier module for high yield low cost manufacturing 设计和开发紧凑型CDMA/WCDMA功率放大器模块，实现高产量低成本制造
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392483
S. Xu, D. Frey, T. Chen, A. Prejs, M. Anderson, J. Miller, T. Arell, M. Singh, R. Lertpiriyapong, A. Parish, R. Schrock, E. Demarest, A. Kini, J. Ryan
{"title":"Design and development of compact CDMA/WCDMA power amplifier module for high yield low cost manufacturing","authors":"S. Xu, D. Frey, T. Chen, A. Prejs, M. Anderson, J. Miller, T. Arell, M. Singh, R. Lertpiriyapong, A. Parish, R. Schrock, E. Demarest, A. Kini, J. Ryan","doi":"10.1109/CSICS.2004.1392483","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392483","url":null,"abstract":"A low cost compact (3 mm /spl times/ 3 mm) internally matched CDMA/WCDMA power amplifier module is designed with high-density-interconnection (HDI) laminate technology. Design methodologies for the power amplifier module are presented. Some advances in wafer processing technology are discussed. The PCS/IMT dual band WCDMA power amplifier achieves a typical 40% power-added-efficiency (PAE) at 27.5 dBm along with a -40 dBc linearity at 5 MHz offset frequency. At a low operating power of 16 dBm, 22% PAE can be achieved at V/sub cc/ = 1.5 V. Manufacturing yield issues are discussed as well.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116938029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry 基于并联电流开关锁存电路的40gb /s全速率4:1多路复用器的低电源电压工作
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392552
Y. Amamiya, Y. Suzuki, Y. Yamazaki, M. Mamada, H. Hida
{"title":"Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry","authors":"Y. Amamiya, Y. Suzuki, Y. Yamazaki, M. Mamada, H. Hida","doi":"10.1109/CSICS.2004.1392552","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392552","url":null,"abstract":"We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126066026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wireless base station technology evolution 无线基站技术演进
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392468
B. Vassilakis, A. Cova, W. Veitschegger
{"title":"Wireless base station technology evolution","authors":"B. Vassilakis, A. Cova, W. Veitschegger","doi":"10.1109/CSICS.2004.1392468","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392468","url":null,"abstract":"Traditional base station architectures are evolving due to market pressures and the need to provide a better quality of service, especially for current and future data services such as those offered by 3G and beyond. The need for flexibility, modularity and low operational cost is driving designers to consider novel architectures, circuit techniques and device technologies. Increasingly, the digital and RF domains are merging in architectures that offer performance and value that was unthinkable before.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Semiconductor technology considerations in high speed data conversion 高速数据转换中的半导体技术考虑
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392477
M. Chang
{"title":"Semiconductor technology considerations in high speed data conversion","authors":"M. Chang","doi":"10.1109/CSICS.2004.1392477","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392477","url":null,"abstract":"When designing low-cost, moderate-performance data converters (ADCs or DACs), CMOS is an almost universal choice. However, as the performance requirements increase and the cost constraints diminish, the choice of technology is not as straightforward. This paper analyzes trade-offs between various IC technologies for high-speed ADC/DAC insertions. These technology considerations may influence circuit designers in technology selection and help process engineers to better understand the relative strengths and weaknesses of their technologies.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129302006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fast low-power 4/spl times/4 switch IC using InP HEMTs for 10-Gbit/s systems 采用InP hemt的快速低功耗4/spl times/4开关IC，适用于10gbit /s系统
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392501
H. Kamitsuna, Y. Yamane, M. Tokumitsu, H. Sugahara, M. Muraguchi
{"title":"A fast low-power 4/spl times/4 switch IC using InP HEMTs for 10-Gbit/s systems","authors":"H. Kamitsuna, Y. Yamane, M. Tokumitsu, H. Sugahara, M. Muraguchi","doi":"10.1109/CSICS.2004.1392501","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392501","url":null,"abstract":"A 4/spl times/4 switch IC using cold-FETs connected in series can be used as a single-ended 4/spl times/4 switch, an add drop multiplexer, or a differential 2/spl times/2 switch. An InP HEMT with a low Ron/spl middot/Coff product enables us to configure a dc-to-over-10-GHz switch without using a shunt FET, which offers a logic-level-independent interface. A packaged IC achieves error-free operation up to 12.5 Gbit/s with either negative (VH = 0 V, VL = -0.9 V) or positive (VH = +13 V, VL = +0.7 V) logic-level input for all 16 possible states. The power consumption is less than 5 mW. The add drop multiplexing operation with an ultra-fast switching of /spl sim/160 ps is also successfully demonstrated.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114808982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel compact composite power cell for high linearity power amplifiers in InGaP HBTs 一种用于高线性度功率放大器的新型紧凑复合电池
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392482
Huai Gao, Haitao Zhang, H. Guan, Li-wu Yang, G. Li
{"title":"A novel compact composite power cell for high linearity power amplifiers in InGaP HBTs","authors":"Huai Gao, Haitao Zhang, H. Guan, Li-wu Yang, G. Li","doi":"10.1109/CSICS.2004.1392482","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392482","url":null,"abstract":"A novel compact composite power cell design employing the circuit feedback concept between the input and output ports of the power transistor is proposed for realizing high linearity and high efficiency power amplifiers. The RF performance is compared between conventional and the novel compact composite power cells using a class A amplifier operating at 1.71 GHz. At the same DC biasing conditions, the composite power cell shows the output power 1 dB compression point improvement over a conventional cell from 18dBm to 23dBm, while its power added efficiency at P1dB point is increased to 47% from 16%. Furthermore, the third order intercept point of the composite transistor PA achieves 7 dB improvement over the conventional PA, from 29 dBm to 36 dBm.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126360631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RF front-end modules in cellular handsets 蜂窝手机中的射频前端模块
IEEE Compound Semiconductor Integrated Circuit Symposium, 2004. Pub Date : 2004-10-24 DOI: 10.1109/CSICS.2004.1392545
Wang-Chang Albert Gu
{"title":"RF front-end modules in cellular handsets","authors":"Wang-Chang Albert Gu","doi":"10.1109/CSICS.2004.1392545","DOIUrl":"https://doi.org/10.1109/CSICS.2004.1392545","url":null,"abstract":"Radio portion of the cellular handsets have evolved from a nearly all-discrete implementation towards a very high level of integration in baseband IC, transceiver ICs and front-end (FE) modules. Integration allows handsets designers to pack more functionalities into a smaller volume with reduced bills of material (BOM) and costs. This paper reviews the FE modules for the 2/sup nd/ generation (2G) handsets followed by a discussion of future trend of FE integration in the emerging multi-band, multi-mode phones for the 2.5G and 3G systems.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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