Y. Amamiya, Y. Suzuki, Y. Yamazaki, M. Mamada, H. Hida
{"title":"基于并联电流开关锁存电路的40gb /s全速率4:1多路复用器的低电源电压工作","authors":"Y. Amamiya, Y. Suzuki, Y. Yamazaki, M. Mamada, H. Hida","doi":"10.1109/CSICS.2004.1392552","DOIUrl":null,"url":null,"abstract":"We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.","PeriodicalId":330585,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry\",\"authors\":\"Y. Amamiya, Y. Suzuki, Y. Yamazaki, M. Mamada, H. Hida\",\"doi\":\"10.1109/CSICS.2004.1392552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.\",\"PeriodicalId\":330585,\"journal\":{\"name\":\"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2004.1392552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2004.1392552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry
We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.