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2014 IEEE International Conference on IC Design & Technology最新文献

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Metallization of a polymer substrate for microfluidic-cooled RF laminates 微流控RF层压板用聚合物基板的金属化
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838591
S. Long, W. M. Dorsey, André A. Adams, G. Huff
{"title":"Metallization of a polymer substrate for microfluidic-cooled RF laminates","authors":"S. Long, W. M. Dorsey, André A. Adams, G. Huff","doi":"10.1109/ICICDT.2014.6838591","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838591","url":null,"abstract":"A new method for metallization of a polymer substrate has been demonstrated. This method allows for RF devices, including integrated circuits, to be fabricated on substrates which may feature microfluidic channels for cooling. Conventional hot-embossing was used to integrate copper mesh into a poly(methyl methacrylate) (PMMA), forming a microwave laminate. The laminate was machined into a microstrip patch antenna with a resonant frequency of 2.916 GHz.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116767198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC Pathfinder3D:一个用于探索3DIC早期热权衡的框架
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838612
S. Priyadarshi, W. R. Davis, P. Franzon
{"title":"Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC","authors":"S. Priyadarshi, W. R. Davis, P. Franzon","doi":"10.1109/ICICDT.2014.6838612","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838612","url":null,"abstract":"Three dimensional integration technologies offer significant potential to improve performance, performance per unit power and integration density. However, increased power density and thermal resistances leading to higher on-chip temperature is imposing several implementation challenges and restricting widespread adaptation of this technology. This necessitates the need for CAD flows and tools facilitating early thermal evaluation of possible 3D design choices and thermal management techniques. This paper presents a CAD flow and associated framework called Pathfinder3D, which facilitates physically-aware system-level thermal simulation of 3DICs. Usage of Pathfinder3D is shown using a case study comparing thermal profiles of 2D and three 3D implementations of a quadcore chip multiprocessor.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a voltage reference circuit based on subthreshold and triode MOSFETs in 90nm CMOS 基于亚阈值三极管mosfet的90纳米CMOS基准电压电路设计
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838605
Mahmood A. Mohammed, K. Abugharbieh, Mahmoud Abdelfattah, Sanad Kawar
{"title":"Design of a voltage reference circuit based on subthreshold and triode MOSFETs in 90nm CMOS","authors":"Mahmood A. Mohammed, K. Abugharbieh, Mahmoud Abdelfattah, Sanad Kawar","doi":"10.1109/ICICDT.2014.6838605","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838605","url":null,"abstract":"This work presents a new design of a precision voltage reference circuit using MOSFET transistor devices operating in the subthreshold region. Also, a triode region MOSFET has been deployed instead of using resistors. The circuit has been designed and simulated in 90 nm CMOS technology. A reference voltage of 281 mV is obtained with Line Sensitivity, LS, of 0.23% in a supply voltage range of (0.8 V-1.65 V). The Temperature Coefficient, TC, is 125 ppm/°C through a temperature range of (0-85) °C The Power Supply Rejection Ratio (PSRR) is -48 dB at 50 Hz and -26 dB at 1 MHz. Finally, the power consumption is 11.31 μW and the coefficient of process variations is 0.29%. The design has been simulated using Synopsys Custom Designer and HSPICE CAD tools.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A sub-threshold eight transistor (8T) SRAM cell design for stability improvement 亚阈值8晶体管(8T) SRAM单元设计，以提高稳定性
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838592
C. Kushwah, S. Vishvakarma
{"title":"A sub-threshold eight transistor (8T) SRAM cell design for stability improvement","authors":"C. Kushwah, S. Vishvakarma","doi":"10.1109/ICICDT.2014.6838592","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838592","url":null,"abstract":"A single ended 8-transistor (8T) static random access memory (SRAM) cell is presented which is designed for sub-threshold operation with improved data stability. The proposed 8T cell involves the breaking-up of feedback between the true storing nodes that enhances the writability of the cell at ultra-low voltage (ULV) power supply (VDD). During read operation, as 8T is isolated from the bit-lines the cell current increases without affecting the true storing node voltages allowing a large number of bit-cells on single bit-line. Proposed 8T achieves 1.3x higher mean of write static noise margin (WSNM) as compared to the conventional upsized 6T (CU-6T) cell for 200 mV power supply. The read time of CU-6T is 1.2x as that of 8T at 200 mV but same for 300 mV to 500 mV. The read power of CU-6T is 8x as that of 8T for 500 mV power supply. The read decoupling makes proposed 8T more immune to read disturb. Consequently the cell is stable against the variations in process parameters. All simulations and layout designs are accomplished using UMC 90 nm CMOS process technology.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134160444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Testing, diagnosis and repair methods for NBTI-induced SRAM faults nbti诱发SRAM故障的检测、诊断和修复方法
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838608
Bao Liu, Chiung-Hung Chen
{"title":"Testing, diagnosis and repair methods for NBTI-induced SRAM faults","authors":"Bao Liu, Chiung-Hung Chen","doi":"10.1109/ICICDT.2014.6838608","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838608","url":null,"abstract":"NBTI is a major SRAM aging mechanism, leading to reduced read and hold static noise margins, and increased soft error rate. The existing techniques including guard banding, on-chip sensor-based detection, and recovery. In this paper, we propose a group of testing, diagnosis, and repair methods for NBTI-induced memory faults. We observe that NBTI leads to SRAM read errors rather than write errors. We propose to identify NBTI-induced memory read errors based on the existing ECC circuitry, differentiate them with soft errors by correction and double checking, and keep them idle for recovery. We further propose an predictive test method for NBTI-induced memory faults by adaptive body biasing. We achieve an adaptive body biasing formula to simulate the NBTI effect. Our experimental results validate the proposed methods and show that they cost little silicon area and power consumption.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131934152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology 新型模块化双向电源开关和自ESD保护，采用28nm UTBB FDSOI先进的CMOS技术
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838590
P. Galy, J. Bourgeat, D. Marin-Cudraz
{"title":"New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology","authors":"P. Galy, J. Bourgeat, D. Marin-Cudraz","doi":"10.1109/ICICDT.2014.6838590","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838590","url":null,"abstract":"The aim of this paper is to introduce a new design of modular bi-directional power switch for 28nm Ultra Thin Body and BOX (UTBB) Full Depleted (FD) SOI advanced CMOS technology and beyond. Moreover, this proposed solution is self-protected against ElectroStatic Discharge (ESD). The first challenge is to obtain a robust symmetrical elementary power device compatible with this technology and with a silicon area optimization. The second one is to provide a new design to trigger this power device. The last challenge is to be efficient in term of ESD robust without additional protection device. These specifications are reached thanks to a Triac (dual back to back SCR) power device in matrix and BIMOS transistors used in a new trigger solution. The study is performed through the 2D-3D TCAD simulation and a test chip is performed in 28nm FDSOI with silicon demonstrator. Measurements are done in DC sweep condition, in high current pulse with 100ms time width. It also includes Transmission Line Pulse (TLP) with 100ns time width to characterize and qualify this design and topology in ESD range time event.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115676488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The POWER8TM processor: Designed for big data, analytics, and cloud environments POWER8TM处理器:专为大数据、分析和云环境而设计
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838618
J. Friedrich, Hung Q. Le, William J. Starke, Jeffrey Stuecheli, B. Sinharoy, E. Fluhr, D. Dreps, V. Zyuban, G. Still, Christopher J. Gonzalez, David Hogenmiller, F. Malgioglio, R. Nett, R. Puri, P. Restle, David Shan, Z. Deniz, D. Wendel, M. Ziegler, Dave W. Victor
{"title":"The POWER8TM processor: Designed for big data, analytics, and cloud environments","authors":"J. Friedrich, Hung Q. Le, William J. Starke, Jeffrey Stuecheli, B. Sinharoy, E. Fluhr, D. Dreps, V. Zyuban, G. Still, Christopher J. Gonzalez, David Hogenmiller, F. Malgioglio, R. Nett, R. Puri, P. Restle, David Shan, Z. Deniz, D. Wendel, M. Ziegler, Dave W. Victor","doi":"10.1109/ICICDT.2014.6838618","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838618","url":null,"abstract":"POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and today's exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open ecosystem for server innovation.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
ALD ZrO2 processes for BEoL device applications 用于BEoL器件应用的ALD ZrO2进程
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838604
W. Weinreich, K. Seidel, P. Polakowski, S. Riedel, L. Wilde, D. Triyoso, M. Nolan
{"title":"ALD ZrO2 processes for BEoL device applications","authors":"W. Weinreich, K. Seidel, P. Polakowski, S. Riedel, L. Wilde, D. Triyoso, M. Nolan","doi":"10.1109/ICICDT.2014.6838604","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838604","url":null,"abstract":"In this paper three different ZrO2 ALD processes are studied as high-k dielectric in BEoL device applications. One metal organic precursor is compared to a halide precursor used with two different oxidizing agents. The structure, composition and morphology of the films are analyzed on bare Si wafers and the electrical properties such as capacitance, leakage and reliability are investigated on fully integrated BEoL decoupling capacitors. One of the halide ALD processes is identified as the most promising candidate for BEoL capacitor applications.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117272874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor 太阳能供电280mv -1.2 v宽工作范围IA-32处理器
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838610
S. Vangal, Shailendra Jain, V. De
{"title":"A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor","authors":"S. Vangal, Shailendra Jain, V. De","doi":"10.1109/ICICDT.2014.6838610","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838610","url":null,"abstract":"Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great promise for applications with strict energy budgets. In the NTV regime, the supply voltage is at or near the switching voltage (Vr) of the transistors. In this region, energy savings on the order of 5x-10x can be realized. This paper summarizes results from application of NTV techniques to a 32-bit Intel Architecture (IA) core in an effort to quantify and overcome the barriers that have historically relegated ultralow-voltage operation to niche markets. The superscalar IA-32 processor core demonstrates reliable ultra-low voltage operation and energy efficient performance across the wide operating range of 280mV to 1.2V. Starting at 1.2V and 915MHz, core voltage and performance scales down to 280mV and 3MHz, reducing total core power consumption from 737mW to merely 2mW. Minimum energy operation is achieved in near-threshold region with the total energy reaching minima of 170pJ/cycle at 0.45V, validating 4.7X improvement in energy efficiency.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131326240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Characterization and modeling of charge trapping: From single defects to devices 电荷俘获的表征与建模:从单一缺陷到器件
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838620
T. Grasser, G. Rzepa, M. Waltl, W. Gös, K. Rott, G. Rott, H. Reisinger, J. Franco, B. Kaczer
{"title":"Characterization and modeling of charge trapping: From single defects to devices","authors":"T. Grasser, G. Rzepa, M. Waltl, W. Gös, K. Rott, G. Rott, H. Reisinger, J. Franco, B. Kaczer","doi":"10.1109/ICICDT.2014.6838620","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838620","url":null,"abstract":"Using time-dependent defect spectroscopy measurements on nanoscale MOSFETs, individual defects have been characterized in much greater detail than ever before. These studies have revealed the existence of metastable defect states which have a significant impact on the capture and emission time constants. For example, these defect states explain the large emission time constants observed in bias temperature measurements as well as the switching behavior of defects sensitive to gate bias changes towards accumulation. By carefully analyzing the properties of the defects contributing to random telegraph noise and the recoverable component of the bias temperature instability, it could be confirmed that both phenomena are due to the same type of defect. The most fundamental property of these defects is that their time constants are widely distributed, leading to the ubiquitous time and frequency dependence. By transferring this knowledge to large area devices, noise as well as the response to bias temperature stress and recovery can be understood in great detail.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127821211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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