2014 IEEE International Conference on IC Design & Technology最新文献_第2页

Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations 通过大规模线程原子瞬态模拟了解BTI/RTN对时间的影响

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838587

D. Rodopoulos, Dimitrios Stamoulis, Grigorios Lyras, D. Soudris, F. Catthoor

引用次数: 12

Modeling SRAM dynamic VMIN SRAM动态VMIN建模

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838609

James Boley, B. Calhoun, V. Chandra, R. Aitken

引用次数: 0

RC triggered active ESD clamps; How should they behave under powered conditions? RC触发有源ESD钳;它们在有动力的条件下应该如何表现?

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838619

James W. Miller, M. Stockinger, Scott Ruth, A. Gerdemann, M. Etherton, M. Moosa

引用次数: 5

Single-ended sub-threshold finfet 7T SRAM cell without boosted supply 无升压电源的单端亚阈值finet 7T SRAM单元

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838593

C. Kushwah, S. Vishvakarma, D. Dwivedi

引用次数: 13

An on-chip high-voltage current sensor for battery module monitoring 用于电池模块监测的片上高压电流传感器

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838585

Chua-Chin Wang, Wen-Je Lu, Sheng-Syong Wang

引用次数: 7

High-performance stacked TiO2-ZrO2 and Si-doped ZrO2 metal-insulator-metal capacitors 高性能堆叠TiO2-ZrO2和掺硅ZrO2金属-绝缘体-金属电容器

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838596

R. Padmanabhan, N. Bhat, Y. Morozumi, S. Mohan, S. Kaushal

{"title":"High-performance stacked TiO2-ZrO2 and Si-doped ZrO2 metal-insulator-metal capacitors","authors":"R. Padmanabhan, N. Bhat, Y. Morozumi, S. Mohan, S. Kaushal","doi":"10.1109/ICICDT.2014.6838596","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838596","url":null,"abstract":"Metal-insulator-metal (MIM) capacitors for DRAM applications have been realised using stacked TiO2-ZrO2(TiO2/ZrO2 and ZrO2/TiO2) and Si-doped ZrO2 (TiO2/Si-doped ZrO2) dielectrics. High capacitance densities (> 42 fF/ μm2), low leakage current densities (<; 5×10-7 A/cm2 at -1 V), and sub-nm EOT (<; 0.8 nm) have been achieved. The effects of constant voltage stress on the device characteristics is studied. The structural analysis of the samples is performed by X-ray diffraction measurements, and this is correlated to the electrical characteristics of the devices. The surface chemical states of the films are analyzed through X-ray photoelectron spectroscopy measurements. The doped-dielectric stack (TiO2/Si-doped ZrO2) helps to reduce leakage current density and improve reliability, with a marginal reduction in capacitance density; compared to their undoped counterparts (TiO2/ZrO2 and ZrO2/TiO2). We compare the device performance of the fabricated capacitors with other stacked high-k MIM capacitors reported in recent literature.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131820258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Highly-reliable TaOx reram technology using automatic forming circuit 采用自动成形电路的高可靠性陶氏工艺

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838600

K. Kawai, A. Kawahara, R. Yasuhara, S. Muraoka, Zhiqiang Wei, R. Azuma, K. Tanabe, K. Shimakawa

{"title":"Highly-reliable TaOx reram technology using automatic forming circuit","authors":"K. Kawai, A. Kawahara, R. Yasuhara, S. Muraoka, Zhiqiang Wei, R. Azuma, K. Tanabe, K. Shimakawa","doi":"10.1109/ICICDT.2014.6838600","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838600","url":null,"abstract":"ReRAM is increasingly being developed for applications that require higher speeds and lower voltages than flash memory. We have found TaOx to have high performance and high reliability. However one of the phenomena observed in ReRAM is that each resistance after Set and Reset varies during every cycle. To stabilize resistive switching, the key is to limit these variations in resistance. In ReRAM, a conductive filament (CF) is created by the forming pulse. Resistive switching in the CF is based on reduction and oxidization using this voltage pulse. This paper reviews a hopping percolation model which we have proposed for the switching process, and this paper proposes an automatic forming circuit using our newly-developed externally-scalable forming pulse (ESF) scheme. In this CF model, conductive paths show different conductivities caused by the formation of different percolation networks that link hopping sites. Larger CFs show greater variation in resistance due to the many possible combinations of percolation networks. This makes it important to develop a forming technique that limits CFs to their optimal size. Forming is based on dielectric breakdown, so the pulse width ranges over approximately three orders. The automatic forming circuit detects, bit by bit, whether forming is over, and stops the forming pulse after a specified period. A forming pulse is then generated, using an external clock, to cover the range of pulse widths. This allows the filament size to be controlled to ensure it is uniform for all of the bits in the circuit, at the cost of only a small area overhead.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology 基于28nm CMOS技术的高速交流耦合串行收发器10gbps信号损耗检测器

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838607

Sanad Kawar, K. Abugharbieh, Waseem Al-Akel, Mahmood A. Mohammed

引用次数: 2

Assessing device reliability through atomic-level modeling of material characteristics 通过材料特性的原子级建模评估器件可靠性

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838622

G. Bersuker

引用次数: 0

32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation 32%的转换率和27%的数据率提高2×VDD输出缓冲使用PVTL补偿

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838601

Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang

引用次数: 3