Modeling SRAM dynamic VMIN

Designing and margining SRAMs in new emerging technologies has become increasingly difficult due to an increase in variation and cache size. In the past, the length of the wordline (WL) pulse width was typically set by the read operation, due to its longer delay. However, in newer technologies it has been shown that in many cases the write operation is more limiting due to the high variability of the minimum sized PMOS device. Measuring the critical WL pulse width (TCRIT) of the write operation requires transient simulation which is more computation intensive, resulting in higher simulation times. In this paper we present a method for measuring write TCRIT which uses sensitivity analysis to provide a ~112X speedup over recursive statistical blockade. In addition, we observe that increasing the WL pulse width allows for a reduction in total cycle time. Using this information, we show that negative BL reduction is more effective at reducing TCRIT compared WL boosting as the cycle time is reduced.