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2014 IEEE International Conference on IC Design & Technology最新文献

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Efficient computation of combinational circuits reliability based on probabilistic transfer matrix 基于概率传递矩阵的组合电路可靠性高效计算
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838588
L. Naviner, Kaikai Liu, Hao Cai, J. Naviner
{"title":"Efficient computation of combinational circuits reliability based on probabilistic transfer matrix","authors":"L. Naviner, Kaikai Liu, Hao Cai, J. Naviner","doi":"10.1109/ICICDT.2014.6838588","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838588","url":null,"abstract":"The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dual function heat-spreading and performance of the IBM/ASTRON DOME 64-bit μServer demonstrator IBM/ASTRON DOME 64位μServer演示器的双功能散热和性能
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838613
R. Luijten, Andreas C. Döring, S. Paredes
{"title":"Dual function heat-spreading and performance of the IBM/ASTRON DOME 64-bit μServer demonstrator","authors":"R. Luijten, Andreas C. Döring, S. Paredes","doi":"10.1109/ICICDT.2014.6838613","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838613","url":null,"abstract":"For the IBM-ASTRON DOME μServer project, we are currently building two types of memory DIMM-like form factor compute node boards. The first is based on a 4 core 2.2 GHz SoC and the second on a 12 core / 24 thread 1.8 GHz SoC. Both employ the 64-bit Power instruction set. Our innovative hot-water based cooling infrastructure also supplies the electrical power to our compute node board. We show initial performance results and conclude with the key lessons we have learnt and an outlook on our next activities.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115545406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Workload prediction for adaptive power scaling using deep learning 基于深度学习的自适应功率扩展的工作负载预测
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838580
Stephen J. Tarsa, Amit Kumar, H. T. Kung
{"title":"Workload prediction for adaptive power scaling using deep learning","authors":"Stephen J. Tarsa, Amit Kumar, H. T. Kung","doi":"10.1109/ICICDT.2014.6838580","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838580","url":null,"abstract":"We apply hierarchical sparse coding, a form of deep learning, to model user-driven workloads based on on-chip hardware performance counters. We then predict periods of low instruction throughput, during which frequency and voltage can be scaled to reclaim power. Using a multi-layer coding structure, our method progressively codes counter values in terms of a few prominent features learned from data, and passes them to a Support Vector Machine (SVM) classifier where they act as signatures for predicting future workload states. We show that prediction accuracy and look-ahead range improve significantly over linear regression modeling, giving more time to adjust power management settings. Our method relies on learning and feature extraction algorithms that can discover and exploit hidden statistical invariances specific to workloads. We argue that, in addition to achieving superior prediction performance, our method is fast enough for practical use. To our knowledge, we are the first to use deep learning at the instruction level for workload prediction and on-chip power adaptation.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115813533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A high-level design rule library addressing CMOS and heterogeneous technologies 解决CMOS和异构技术的高级设计规则库
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838599
G. Cibrario, M. Gary, F. Gays, Karim Azizi-Mourier, O. Billoint, O. Turkyilmaz, O. Rozeau
{"title":"A high-level design rule library addressing CMOS and heterogeneous technologies","authors":"G. Cibrario, M. Gary, F. Gays, Karim Azizi-Mourier, O. Billoint, O. Turkyilmaz, O. Rozeau","doi":"10.1109/ICICDT.2014.6838599","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838599","url":null,"abstract":"Physical verification of an integrated circuit is a crucial step before manufacturing. In order to ensure the correctness of a design regarding the whole process flow, Design Rule Checking (DRC) is mandatory. As transistor size is reduced, the number of design rules to check increases exponentially. The increasing number of metal layers and heterogeneous integration possibilities are generating rules duplication, thus leading to a significant risk of mistakes, therefore being a relevant parameter to consider. This paper presents a new approach to write design rules using a high-level description language, offering noticeable modularity and reusability, available through a generic Design Rule Library (DRL) concept. This methodology fastens and simplifies DRC rules file writing by allowing substantial reduction of the number of lines to be hand written.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117224353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits 异步电路3D-IC分划方案的比较分析
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838586
L. Caley, C. Lo, Francis Sabado, J. Di
{"title":"A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits","authors":"L. Caley, C. Lo, Francis Sabado, J. Di","doi":"10.1109/ICICDT.2014.6838586","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838586","url":null,"abstract":"In an attempt to further extend Moore's Law, circuit designers are turning to three-dimensional integrated circuit (3D-IC) design. However, stacking active devices presents new design challenges, the most notable being thermal dissipation. When paired with a delay-insensitive asynchronous circuit design technique such as NULL Convention Logic (NCL), the two technologies unite to solve the inherent weaknesses of each other. As part of the 3D-IC design process, a circuit must be partitioned evenly between the stacked wafers. This study presents three strategies to split an NCL circuit into two die, in an attempt to discover the optimal partitioning method for asynchronous circuits. Analysis is done on total interconnect length, number of thru-silicon vias required, and circuit area.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pull-up/pull-down line impedance matching methodology for high speed transmitters 高速变送器的上拉/下拉线路阻抗匹配方法
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838589
A. Durgaryan, Abraham Balabanyan, Vazgen Melikyan, K. Abugharbieh
{"title":"Pull-up/pull-down line impedance matching methodology for high speed transmitters","authors":"A. Durgaryan, Abraham Balabanyan, Vazgen Melikyan, K. Abugharbieh","doi":"10.1109/ICICDT.2014.6838589","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838589","url":null,"abstract":"A design and simulations methodology that detects and compensates for NMOS and PMOS transistor resistance variation is presented. The proposed methodology provides a robust mechanism to match the transmitter impedance to the line impedance which minimizes reflection and improves signal quality. A mixed signal approach, where an analog circuit detects the resistance variation, and a digital circuit uses the data to control the analog compensation circuit, is used. The system is designed in 28 nm CMOS process and simulated using Synopsys mixed mode simulation tools. Simulations show that worst case mismatch due to process, voltage and temperature variation is 2.7%.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116668374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
3D serial TSV link for low-power chip-to-chip communication 用于低功耗芯片对芯片通信的3D串行TSV链路
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838583
Giulia Beanato, A. Cevrero, G. Micheli, Y. Leblebici
{"title":"3D serial TSV link for low-power chip-to-chip communication","authors":"Giulia Beanato, A. Cevrero, G. Micheli, Y. Leblebici","doi":"10.1109/ICICDT.2014.6838583","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838583","url":null,"abstract":"3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances area consumption and energy efficiency. Using 10μm-diameter TSV technology, an 8Gb/s serial link consumes only 84fJ/bit with 10X area reduction over 8b parallel bus.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122571898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Emerging research device roadmap and perspectives 新兴研究设备路线图和前景
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838616
An Chen
{"title":"Emerging research device roadmap and perspectives","authors":"An Chen","doi":"10.1109/ICICDT.2014.6838616","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838616","url":null,"abstract":"The challenges in CMOS scaling have motivated research on a wide range of emerging devices, to extend the life of CMOS or to explore beyond-CMOS applications. The Emerging Research Device (ERD) chapter in ITRS systematically tracks and assesses numerous novel device options for both memory and logic applications. Most emerging devices explored so far are more suitable to augment CMOS than to replace CMOS. To truly utilize the unique characteristics of emerging devices, a system approach with device-design co-optimization needs to be adopted. Novel architectures may find promising opportunities in the beyond-CMOS domain.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Mobile CPU power/performance benchmarking and process technology co-optimization 移动CPU功耗/性能基准测试和流程技术协同优化
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838611
R. Bucki, Todd Bridges, B. Bowers, T. Xue, I. Mir, D. Le, T. Kazi, J. Fischer, S. Ekbote, S. Sengupta, G. Nallapati
{"title":"Mobile CPU power/performance benchmarking and process technology co-optimization","authors":"R. Bucki, Todd Bridges, B. Bowers, T. Xue, I. Mir, D. Le, T. Kazi, J. Fischer, S. Ekbote, S. Sengupta, G. Nallapati","doi":"10.1109/ICICDT.2014.6838611","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838611","url":null,"abstract":"The form factor of mobile devices and their associated thermal dissipation characteristics present practical limits to SoC (and specifically CPU) power consumption. Multiple maximum temperature constraints interact with the thermal “time constant” of package and product to limit allowable die temperature. This can constrain maximum CPU frequency in real use cases. The co-design of product and process technology is required to maximize thermally constrained performance. Technology features, device Ieff/Ioff setpoints, and circuit design styles are all levers to optimize thermally constrained performance. A methodology for early prediction of product sensitivities to these levers is required to enable their definition sufficiently early in the development cycle of the technology node.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Robust low-power reconfigurable computing with a variation-aware preferential design approach 基于变化感知优先设计方法的鲁棒低功耗可重构计算
2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838621
Somnath Paul, S. Mukhopadhyay, S. Bhunia
{"title":"Robust low-power reconfigurable computing with a variation-aware preferential design approach","authors":"Somnath Paul, S. Mukhopadhyay, S. Bhunia","doi":"10.1109/ICICDT.2014.6838621","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838621","url":null,"abstract":"Reconfigurable hardware platforms, such as Field Programmable Gate Arrays (FPGA), are being increasingly used in diverse embedded applications. These platforms often use high-density memory array, which suffer from variation-induced parametric failures. Such failures lead to incorrect operation and hence, loss in output quality for many signal processing applications. In this paper, we propose a preferential design approach at both application mapping and circuit level, which can significantly improve output quality as well as energy efficiency for signal processing applications under large parameter variations. The proposed mapping process considers the reliability map of a memory array and maps the important operations with respect to output quality to more reliable memory blocks under performance constraint. At circuit level, we exploit the read-dominant memory access pattern in reconfigurable platforms to skew the memory cells for better read stability leading to improved quality. Such an architecture/circuit co-design approach can also tolerate increased failure rate at low operating voltage, thus facilitating low-power operation.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128172365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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