Pull-up/pull-down line impedance matching methodology for high speed transmitters

Abstract

A design and simulations methodology that detects and compensates for NMOS and PMOS transistor resistance variation is presented. The proposed methodology provides a robust mechanism to match the transmitter impedance to the line impedance which minimizes reflection and improves signal quality. A mixed signal approach, where an analog circuit detects the resistance variation, and a digital circuit uses the data to control the analog compensation circuit, is used. The system is designed in 28 nm CMOS process and simulated using Synopsys mixed mode simulation tools. Simulations show that worst case mismatch due to process, voltage and temperature variation is 2.7%.