A high-level design rule library addressing CMOS and heterogeneous technologies

Abstract

Physical verification of an integrated circuit is a crucial step before manufacturing. In order to ensure the correctness of a design regarding the whole process flow, Design Rule Checking (DRC) is mandatory. As transistor size is reduced, the number of design rules to check increases exponentially. The increasing number of metal layers and heterogeneous integration possibilities are generating rules duplication, thus leading to a significant risk of mistakes, therefore being a relevant parameter to consider. This paper presents a new approach to write design rules using a high-level description language, offering noticeable modularity and reusability, available through a generic Design Rule Library (DRL) concept. This methodology fastens and simplifies DRC rules file writing by allowing substantial reduction of the number of lines to be hand written.