2014 IEEE International Conference on IC Design & Technology最新文献_第5页

STI fill effect on poly-poly comb IL 聚-聚梳子IL的填充效果

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838581

T. Dao, T. Roggenbauer, Jim Colclasure

引用次数: 0

Thermal-driven 3D floorplanning using localized TSV placement 热驱动3D地板规划使用本地化的TSV安置

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838582

Puskar Budhathoki, Andreas Henschel, I. Elfadel

{"title":"Thermal-driven 3D floorplanning using localized TSV placement","authors":"Puskar Budhathoki, Andreas Henschel, I. Elfadel","doi":"10.1109/ICICDT.2014.6838582","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838582","url":null,"abstract":"While 3D-ICs help to improve circuit performance and energy efficiency through the reduction of average wirelength and the increase in communication bandwidth of on-chip wiring, their thermal management remains one of the most challenging obstacles to their productization. Placement of thermal through-silicon-vias (TSVs) has been proposed to improve the vertical heat flow in the chip stack and this alleviate the negative impact of heat dissipation on chip performance and reliability. In this paper, we present a novel physical design flow that integrates thermal-driven 3D floorplanning with a novel algorithm for thermal TSVs placement that we call localized TSV placement. The essence of the algorithm is to analyze the layered thermal map of the chip stack and then insert thermal TSVs iteratively until the maximal on-chip temperature is below a pre-selected target. The algorithm is implemented within a full flow for thermal-driven 3D floorplanning. The implementation is tested using several standard benchmarks for physical design, and the experimental results show the suitability of our algorithm for significantly reducing maximum chip temperature at reasonable density levels for thermal TSVs (100° Kelvin reduction at 0.5% TSV density). The larger the die size, the more beneficial the localized placement of thermal TSV's.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Design layout optimization in the presence of proximity-dependent stress effects 存在邻近依赖应力效应时的设计布局优化

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838594

A. Sultan, R. Ramzan, D. Wristers

引用次数: 2

Random telegraph noise as a new measure of plasma-induced charging damage in MOSFETs 随机电报噪声作为等离子体诱导mosfet充电损伤的新测量方法

2014 IEEE International Conference on IC Design & Technology Pub Date : 2014-05-28 DOI: 10.1109/ICICDT.2014.6838598

M. Kamei, Y. Takao, K. Eriguchi, K. Ono

{"title":"Random telegraph noise as a new measure of plasma-induced charging damage in MOSFETs","authors":"M. Kamei, Y. Takao, K. Eriguchi, K. Ono","doi":"10.1109/ICICDT.2014.6838598","DOIUrl":"https://doi.org/10.1109/ICICDT.2014.6838598","url":null,"abstract":"Random telegraph noise (RTN) has been recently of great importance in designing ultimately scaled MOSFETs. We address in this paper how RTN characteristics are altered by plasma process-induced charging damage (PCD). MOSFETs with SiO2 and high-k gate dielectric were prepared and exposed to an inductively coupled plasma (ICP) with Ar gas. From the time evolution of Ids fluctuation defined as Ids/μIds, where μIds is the mean Ids, we comprehensively investigated the details of RTN features such as the statistical distribution of Ids/μIds, power spectral density, and the time constants for carrier capture and emission. It was found that the statistical distribution width of Ids/μIds, δ(Ids/μIds), increased by PCD for both MOSFETs with the SiO2 and high-k gate dielectrics, suggesting that RTN characteristics can be used as a potential measure of PCD. These features were consistent with Δ Vth results. However, the slope in power spectral density and the time constants exhibited complicated behaviors owing to the nature of created traps by PCD. It is confirmed that PCD alters RTN characteristics, and that, in evaluating the amount of PCD, δ(Ids/μIds) should be used as a straightforward measure.","PeriodicalId":325020,"journal":{"name":"2014 IEEE International Conference on IC Design & Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129758380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1