Design layout optimization in the presence of proximity-dependent stress effects

In this paper, we present Minimized Layout Effect (MINLAYEF) guidelines for reducing the layout and process variations in critical analog circuits. We also present digital design guidelines to minimize the effect of process variations by eliminating stress sources. We also propose a layout for a reference device for a dual stress liner (DSL) device architecture to improve the accuracy of simulations. Si results from circuit layout designed with and without layout guidelines are also presented.