A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits

In an attempt to further extend Moore's Law, circuit designers are turning to three-dimensional integrated circuit (3D-IC) design. However, stacking active devices presents new design challenges, the most notable being thermal dissipation. When paired with a delay-insensitive asynchronous circuit design technique such as NULL Convention Logic (NCL), the two technologies unite to solve the inherent weaknesses of each other. As part of the 3D-IC design process, a circuit must be partitioned evenly between the stacked wafers. This study presents three strategies to split an NCL circuit into two die, in an attempt to discover the optimal partitioning method for asynchronous circuits. Analysis is done on total interconnect length, number of thru-silicon vias required, and circuit area.