A sub-threshold eight transistor (8T) SRAM cell design for stability improvement

Abstract

A single ended 8-transistor (8T) static random access memory (SRAM) cell is presented which is designed for sub-threshold operation with improved data stability. The proposed 8T cell involves the breaking-up of feedback between the true storing nodes that enhances the writability of the cell at ultra-low voltage (ULV) power supply (VDD). During read operation, as 8T is isolated from the bit-lines the cell current increases without affecting the true storing node voltages allowing a large number of bit-cells on single bit-line. Proposed 8T achieves 1.3x higher mean of write static noise margin (WSNM) as compared to the conventional upsized 6T (CU-6T) cell for 200 mV power supply. The read time of CU-6T is 1.2x as that of 8T at 200 mV but same for 300 mV to 500 mV. The read power of CU-6T is 8x as that of 8T for 500 mV power supply. The read decoupling makes proposed 8T more immune to read disturb. Consequently the cell is stable against the variations in process parameters. All simulations and layout designs are accomplished using UMC 90 nm CMOS process technology.