E. Marinissen, M. Konijnenburg, J. Verbree, Chun-Chuan Chi, Sergej Deutsch, C. Papameletis, Tobias Burgherr, K. Shibin, B. Keller, V. Chickermane, S. Goel
{"title":"3D Design‐for‐Test Architecture","authors":"E. Marinissen, M. Konijnenburg, J. Verbree, Chun-Chuan Chi, Sergej Deutsch, C. Papameletis, Tobias Burgherr, K. Shibin, B. Keller, V. Chickermane, S. Goel","doi":"10.1002/9783527697052.CH12","DOIUrl":"https://doi.org/10.1002/9783527697052.CH12","url":null,"abstract":"IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126047805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3D Stacked DRAM Memories","authors":"C. Weis, Matthias Jung, N. Wehn","doi":"10.1002/9783527697052.CH8","DOIUrl":"https://doi.org/10.1002/9783527697052.CH8","url":null,"abstract":"","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127450153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sergej Deutsch, Brandon Noia, K. Chakrabarty, E. Marinissen
{"title":"Optimization of Test‐Access Architectures and Test Scheduling for 3D ICs","authors":"Sergej Deutsch, Brandon Noia, K. Chakrabarty, E. Marinissen","doi":"10.1002/9783527697052.CH13","DOIUrl":"https://doi.org/10.1002/9783527697052.CH13","url":null,"abstract":"This chapter presents a method for robust optimization of 3D test architecture and test scheduling in the presence of input parameter variations. It lists examples of uncertainties in input parameters for 3D test architecture optimization and test scheduling. The chapter then formulates an integer linear programming (ILP) model for robust optimization of 3D test architecture. A recent work has formulated a mathematical model for robust optimization of 3D test architecture and test scheduling and proposed a heuristic based on simulated annealing in order to solve the robust optimization problem for realistic 3D‐ICs. This chapter presents simulation results to evaluate the proposed heuristic method for robust optimization. The framework is implemented in C++. The chapter demonstrates the effect of robust optimization using a simple example. It also shows simulation results obtained with publicly available benchmarks.","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126568538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Cron, E. Marinissen, S. Goel, T. McLaurin, S. Bhatia
{"title":"IEEE Std P1838: 3D Test Access Standard Under Development","authors":"A. Cron, E. Marinissen, S. Goel, T. McLaurin, S. Bhatia","doi":"10.1002/9783527697052.ch14","DOIUrl":"https://doi.org/10.1002/9783527697052.ch14","url":null,"abstract":"IEEE Std P1838 is striving to implement a flexible architecture, allowing access to die‐level DfT structures embedded within a stack of die. Access to these structures should be available at the die level, through all levels of manufacturing as each die is stacked upon the next, and finally at the package level.","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133950011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Green, V. Sahu, Yuanchen Hu, Y. Joshi, A. Fedorov
{"title":"Passive and Active Thermal Technologies: Modeling and Evaluation","authors":"C. Green, V. Sahu, Yuanchen Hu, Y. Joshi, A. Fedorov","doi":"10.1002/9783527697052.CH17","DOIUrl":"https://doi.org/10.1002/9783527697052.CH17","url":null,"abstract":"","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130447625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Index","authors":"","doi":"10.1002/9783527697052.index","DOIUrl":"https://doi.org/10.1002/9783527697052.index","url":null,"abstract":"","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132726329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yang Zhang, Hanju Oh, Yue Zhang, Li Zheng, G. May, Muhannad S. Bakir
{"title":"Thermal Isolation and Cooling Technologies for Heterogeneous 3D‐ and 2.5D‐ICs","authors":"Yang Zhang, Hanju Oh, Yue Zhang, Li Zheng, G. May, Muhannad S. Bakir","doi":"10.1002/9783527697052.CH16","DOIUrl":"https://doi.org/10.1002/9783527697052.CH16","url":null,"abstract":"","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"4 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120912346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Brunschwiler, G. Schlottig, C. L. Ong, B. Burg, A. Sridhar
{"title":"On the Thermal Management of\u0000 3D\u0000 ‐\u0000 ICs\u0000 : From Backside to Volumetric Heat Removal","authors":"T. Brunschwiler, G. Schlottig, C. L. Ong, B. Burg, A. Sridhar","doi":"10.1002/9783527697052.CH19","DOIUrl":"https://doi.org/10.1002/9783527697052.CH19","url":null,"abstract":"","PeriodicalId":323630,"journal":{"name":"Handbook of 3D Integration","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127107188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}