Optimization of Test‐Access Architectures and Test Scheduling for 3D ICs

This chapter presents a method for robust optimization of 3D test architecture and test scheduling in the presence of input parameter variations. It lists examples of uncertainties in input parameters for 3D test architecture optimization and test scheduling. The chapter then formulates an integer linear programming (ILP) model for robust optimization of 3D test architecture. A recent work has formulated a mathematical model for robust optimization of 3D test architecture and test scheduling and proposed a heuristic based on simulated annealing in order to solve the robust optimization problem for realistic 3D‐ICs. This chapter presents simulation results to evaluate the proposed heuristic method for robust optimization. The framework is implemented in C++. The chapter demonstrates the effect of robust optimization using a simple example. It also shows simulation results obtained with publicly available benchmarks.