2015 10th International Design & Test Symposium (IDT)最新文献

{"title":"Revolutionizing validation: The Intel approach for TTM","authors":"Ra'ed Al-Omari, Shahil Rais","doi":"10.1109/IDT.2015.7396728","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396728","url":null,"abstract":"Summary form only given. Intel is focused on gaining a foothold in the burgeoning mobile/IOT computing market. One of the unique challenges in this dynamic market is the aggressive time-to-market (TTM) requirement. In the past, the length of the silicon validation stage for Intel SoCs contributed to the company's inability to deliver products on time, taking up to two years for prior projects. To address this situation, the Devices System Validation group set a transformation goal to reduce time from first silicon to PRQ for base and derivative products. While a validation execution strategy can be optimized based on perceived risk in changes to HW, FW, and SW, accounting for silicon debug is far more difficult. It is nearly impossible to predict the amount of time necessary to debug the breadth and quantity of issues (Sightings) that will be found during execution. The number of sightings generated over the course of a project depends on many factors, including the health of the RTL and process, the stability of the FW and SW code base, and the technical strength of the execution team. This unpredictability results in many challenges when attempting to hit a target time window from first silicon to Production Ready Quality (PRQ). Moorefield, a platform based on Intel's 22 nm Atom-based SoC named Anniedale, was the first project to achieve a goal of first silicon to Production in two quarters. A major factor in this achievement was the strategy employed by the team to manage the risk in silicon validation and debug with aggressive shift left effort that included early and close collaboration with the customer, platform, and design teams. This strategy is built on several key pillars. 1) Comprehensive Design for Debug (DFD) features and tools that are fully validation in pre-silicon & emulation to prepare for critical debug scenarios at customer platforms. 2) Early and close engagement with the lead customer and platform teams to develop an alpha level quality SW in emulation. 3) Employing requirements-based validation to focus on validating only the form factor OS application use-cases. 4) A strict platform regressions strategy that can be scaled from pre to post silicon 5) Centralized System Debug organization to accelerate time to closure of critical sightings. In this talk we will be detailing and presenting the innovative strategies the System Validation (SV) organization took around the these pillars to achieve a successful launch of the Moorefield-based Asus tablet and phone in record breaking time.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"25 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114099757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem","authors":"A. Bellemou, M. Anane, N. Benblidia, M. Issad","doi":"10.1109/IDT.2015.7396750","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396750","url":null,"abstract":"This paper presents the Hardware/Software (HW/SW) implementation of Scalar Multiplication (SM) for Elliptic Curve Cryptosystem (ECC) over prime field Fp At low level of abstraction, the SM execution is based on the Modular Addition Subtraction (MAS) and the Modular Multiplication (MM) operations. In this work, we propose the implementation of the SM as a Programmable System on Chip (PSoC), using the MicroBlaze soft processor core of Xilinx. In the proposed embedded system, the control of the SM algorithm is executed by the embedded processor, while the MASs and the MMs are computed within specific hardware. The results show that the execution time of 160-bits and 256-bits SM are respectively about 700ms and 1354ms. The architecture requires only 1960 occupied slices.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123201247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memory profiling for intra-application data-communication quantification: A survey","authors":"I. Ashraf, M. Taouil, K. Bertels","doi":"10.1109/IDT.2015.7396732","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396732","url":null,"abstract":"With the advent of technology, multi-core architectures are prevalent in embedded, general-purpose as well as high-performance computing. Efficient utilization of these platforms in an architecture agnostic way is an extremely challenging task. Hence, profiling tools are essential for programmers to optimize the applications for these architectures and understand the bottlenecks. Typical bottlenecks are irregular memory-access patterns and data-communication among cores which may reduce anticipated performance improvement. In this study, we first survey the memory-access optimization profilers. Thereafter, we provide a detailed comparison of data-communication profilers and highlight their strong and weak aspects. Finally, recommendations for improving existing data-communication profilers and/or designing future ones are thoroughly discussed.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124702528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST","authors":"A. Abu-Issa, Iyad Tumar, Wasel T. Ghanem","doi":"10.1109/IDT.2015.7396748","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396748","url":null,"abstract":"This paper presents the use of switch-tail ring counter as low transition test pattern generator (TPG) to reduce power consumption in test-per-clock and test-per-scan built-in self-test (BIST) applications. The proposed TPG is implemented by dividing the register in the test mode into many switch-tail ring counters. These counters are fed with a seed in such a way to produce a single transition between consecutive test patterns. Also each of these ring counters are triggered with a clock and control signal such that not all the counters are triggered with each clock in order to reduce the switching activity in the inputs of the circuit-under-test (CUT). The proposed technique can be used for test-per-clock and test-per-scan BIST. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for ISCAS'85 (test-per-clock) and for the ISCAS'89 (test-per-scan) benchmark circuits show that the proposed design can reduce the switching activity with an average of 84% and 72%, respectively.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122436849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A bi-objective heuristic for heterogeneous MPSoC design space exploration","authors":"B. Mediouni, S. Niar, R. Benmansour, K. Benatchba, M. Koudil","doi":"10.1109/IDT.2015.7396742","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396742","url":null,"abstract":"Recent technology advances allow new generation reconfigurable-based embedded systems to contain a large number of cores and reconfigurable logic elements. Consequently, to take benefit of such very powerful hybrid reconfigurable MPSoC, designers need tools to explore the large design space of the possible configurations. In this paper, we develop a new hybrid bi-objective genetic and parallel variable neighborhood descent algorithm (GA-PVNS) to determine close to optimal configurations for heterogeneous FPGA-based MPSoC (Ht-MPSoC). Our exploration method aims to optimize simultaneously two objectives, namely area on the FPGA and execution time, taking advantage of the Genetic Algorithm (GA) diversification ability and the intensification provided by Variable Neighborhood Search (VNS) algorithm. Our design space includes Ht-MPSoC with private and shared HW accelerators on FPGA. Compared to exact methods, our algorithm determines very satisfactory multi-objective configurations in a very reduced execution time.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129053636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable test platform for modular embedded systems in manufacturing processes","authors":"S. Folea, S. Enyedi, L. Miclea, H. Hedesiu","doi":"10.1109/IDT.2015.7396739","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396739","url":null,"abstract":"This paper presents a platform developed for in production testing of modular embedded systems. These systems are flexible and low cost, with respect to production and maintenance. However, they require a complex testing process, in order to reduce the flaws in the production process and increase the rate of certified modules. For the manufacturers, modular embedded systems offer the possibility of reusing parts of a project in other projects, thus reducing the overall cost. Being reconfigurable, these systems enable the manufacturers to sell devices that fit the requirements of more users.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116894117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Obfuscated arbitrary computation using cryptographic primitives","authors":"N. G. Tsoutsos, M. Maniatakos","doi":"10.1109/IDT.2015.7396726","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396726","url":null,"abstract":"The breakthrough of fully homomorphic encryption (FHE) enables privacy-preserving arbitrary computation in the cloud, supporting both addition and multiplication over encrypted data. Current FHE implementations, however, suffer from high performance overheads and require expensive boot-strapping operations to decrease ciphertext noise. In this work, we discuss how homomorphic encryption primitives can implement a functionally complete set of homomorphic operations and enable arbitrary computation that is outsourced by a single party. We focus on obfuscated computation with or without special look-up tables, to enable branch decisions over encrypted values while preserving privacy. Since partial homomorphic encryption is orders of magnitude less expensive than FHE, it can be more practical for privacy-preserving applications in the cloud.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"60 25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design constraints and challenges behind fault tolerance systems in a mobile application framework","authors":"Venkata N. Inukollu, Taeghyun Kang, N. Sakhnini","doi":"10.1109/IDT.2015.7396760","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396760","url":null,"abstract":"Mobile applications are a part of human life, ranging from simple tasks such as e-mails to critical operations such as security surveillances. Referable to the different softwares and hardwares used in mobile devices, failure of a mobile application is unavoidable. Failure of mobile applications poses a serious threat to the success of a mobile software. Also, those failures can result in a great loss to the end users who use mission critical applications (such as banking apps). In this paper, we discuss about the emergence of mobile apps from simple to complex applications, failures (software & hardware) in mobile apps, design constraints, and challenges associated with fault tolerance systems.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127792493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SimEvents based high level early design space exploration and modeling of a 3D Network on Chip","authors":"Nejib Mediouni, Samir Ben Abid, O. Kallel, S. Hasnaoui","doi":"10.1109/IDT.2015.7396759","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396759","url":null,"abstract":"The transition from 2D to 3D Network on Chips is have recently gained momentum with research effort targeted to solving the different implementation issues. The planification and design space exploration for 3D NoCs, intuitively harder than for 2D NoCs, calls for more flexible and powerful simulation tools. The Matlab ecosystem is appropriate for the implementation of such simulation systems. In this paper, we present the simulation of a model of a mesh 4 × 4 × 3 3D NoC using SimEvents, a Discrete Event Simulation accessible through Mathworks Simulink. The performance of the whole NoC is measured for the whole network, and for the side, corner, and middle nodes.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127655923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic test pattern generation for virtual hardware model using constrained symbolic execution","authors":"Nahla Mohamed, M. Safar, A. Wahba, A. Salem","doi":"10.1109/IDT.2015.7396755","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396755","url":null,"abstract":"Symbolic execution is widely used for analyzing software behavior, generating test pattern, and finding bugs. However, it is not feasible for large programs. Symbolic execution attempts to explore each path of the program which result in a path explosion for large programs. This paper introduces a framework that makes the symbolic execution practical for the virtual HW models that run on QEMU platform. We describe an approach that can symbolically execute a virtual HW model to automatically generate selective test patterns. We use the constraints-based technique in order to show preferences for the generated test pattern. A native symbolic run of the program along with the constraints will generate test patterns correspond to every possible path. Our technique adds assertion statement into the program to indicate a specific operation mode for the device that the developer pay attention on. The symbolic engine generates test patterns that can derive the program through all feasible paths to reach the assertion. These test patterns can be used to verify same operation mode on the associated HW RTL model.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121031573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}