2015 10th International Design & Test Symposium (IDT)最新文献_第3页

Transforming between logic locking and IC camouflaging 逻辑锁定与IC伪装之间的转换

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396725

Muhammad Yasin, O. Sinanoglu

引用次数: 37

Guiding intelligent testbench automation using data mining and formal methods 利用数据挖掘和形式化方法指导智能试验台自动化

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396737

Eman El Mandouh, A. Wassal

{"title":"Guiding intelligent testbench automation using data mining and formal methods","authors":"Eman El Mandouh, A. Wassal","doi":"10.1109/IDT.2015.7396737","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396737","url":null,"abstract":"Achieving coverage closure is consistently identified as one of the most difficult challenges during the functional verification of today's HW designs. Constraint random testing as well as coverage directed test generation (CDTG) techniques have been proposed previously with different degree of success. This paper presents a framework for speeding up the coverage closure of the design under verifications (DUV) using state of the art verification techniques. The framework starts with random simulation of the DUV followed by frequent pattern mining of simulation data to extract some valid design constraints. Simulation coverage database is analyzed and the coverage holes are identified and directed to the formal verification step, formal analysis is used to prove the unreachability of some coverage holes during simulation run. Formally proven unreachable cover items as well as automatically extracted design constraints are then fed as test template specification to direct the intelligent testbench generation to rapidly achieve the coverage of previously uncovered corner cases. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of today's RTL designs.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125910632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reliability degradation in the scope of aging — From physical to system level 老化范围内的可靠性退化-从物理到系统级别

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396727

H. Amrouch, J. Henkel

引用次数: 5

Multiple fault testing in systems-on-chip with high-level decision diagrams 基于高级决策图的片上系统多故障测试

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396738

R. Ubar, S. Oyeniran, Mario Schölzel, H. Vierhaus

引用次数: 10

Efficient data management on 3D stacked memory for big data applications 面向大数据应用的3D堆叠内存高效数据管理

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396741

Cheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang

{"title":"Efficient data management on 3D stacked memory for big data applications","authors":"Cheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang","doi":"10.1109/IDT.2015.7396741","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396741","url":null,"abstract":"Big data processing has been an increasingly important field which has attracted a lot of attention from academia and industry. However, it worsens the memory wall problem for processor design, which means a large performance gap between processor computation and memory access. The 3D stacked memory structure has been put forward as a promising method to relieve this problem. As non-volatile memory(NVM) become available and common nowadays, they can be fused into the 3D memory structure to provide a fast and large memory. DRAM + NVM have been designed as a novel, faster and larger memory structure. Flash is the maturest NVM material currently so that flash takes the role of NVM in our experiment. However, as DRAM has totally different characteristics from Flash, such combined structure shows bad support for big data applications. Thus, efficient data manage strategies are greatly needed. We implemented two data manage strategies(granularity strategy (GS) and Read/Write partition strategy (RWPS)) to improve performance. Our experiment results are very positive. When using 64 channels, GS can improve performance by 11.3%, and the RWPS can improve performance by 20.4%. Combined the two strategies together, the performance can be increased by 26.1%. In addition, for RWPS, it can obviously increase the write performance by 29.8% because of its novel design.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114745679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High level NoC modeling using discrete event simulation 使用离散事件模拟的高级NoC建模

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396752

Nejib Mediouni, Samir Ben Abid, O. Kallel, S. Hasnaoui

引用次数: 1

Heterogeneous multi-core architecture for a 4G communication in high-speed railway 高速铁路4G通信的异构多核架构

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396731

M. Makni, M. Baklouti, S. Niar, M. Biglari-Abhari, M. Abid

引用次数: 11

An automatic ECG generator for testing and evaluating ECG sensor algorithms 用于测试和评估心电传感器算法的自动心电发生器

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396740

H. A. Hamadi, A. Gawanmeh, M. Al-Qutayri

{"title":"An automatic ECG generator for testing and evaluating ECG sensor algorithms","authors":"H. A. Hamadi, A. Gawanmeh, M. Al-Qutayri","doi":"10.1109/IDT.2015.7396740","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396740","url":null,"abstract":"The use of biomedical sensors, be it attached or embedded inside a human body, to monitor various physiological parameters is increasing at a significant rate due to continued advances in miniaturizations and materials. Testing and verification of the algorithms used in processing the physiological parameters of concern is essential, given the sensitivity of their usage. Simulation is a technique that is widely used to achieve this. However, proper test cases are required in order to carry out the simulation process. ElectroCardioGram (ECG) is one of the most commonly used and studied physiological signal, yet, algorithms that handle ECG recorded data are not being tested and verified thoroughly due to the lack of proper test cases. This paper presents an automatic test case generation algorithm that can be used to provide ECG records for testing purposes. The algorithm is based on a range of the parameters related ECG components such as amplitude, duration, slope, and physical characteristics. Hence, the required shape of the ECG can be controlled in order to be able to cover a wide range of scenarios during testing. We provide an implementation of the algorithm and illustrate it on two different ECG sensor algorithms.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125688126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Testing of 3D IC with minimum power using genetic algorithm 基于遗传算法的最小功耗3D集成电路测试

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396746

Tanusree Kaibartta, D. K. Das

{"title":"Testing of 3D IC with minimum power using genetic algorithm","authors":"Tanusree Kaibartta, D. K. Das","doi":"10.1109/IDT.2015.7396746","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396746","url":null,"abstract":"System-on-a-chip (SOC) uses embedded cores those require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. Optimization of TAM and test time at SOC level is an important area of research. However, the interconnect between the cores of SOC contribute to circuit delay and power consumption. Power and thermal issues are major concern, specially during testing the design under test (DUT) consumes significantly more power in test mode than in normal operation. To reduce the interconnect 3D IC is a solution where multiple device layers are stacked together. The problem of high test power consumption can be solved by the use of power aware test planning in 3D IC. In this paper, we have addressed the problem and proposed genetic algorithm based approach for power aware test planning. Given a TAM width available to test a SOC, our algorithm partitions this width into different groups and places the cores of these groups in different layers in core based SOCs based on 3D IC technology with the goal to optimize the total test time under certain power limit. In addition to this our technique also takes into account minimum power during testing, where the goal is to optimize the total test time with minimum power. The experimental results establish the effectiveness of our algorithm.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Chip-level programming of heterogeneous multiprocessors 异构多处理器的芯片级编程

2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396730

Mwaffaq Otoom, J. M. Paul

引用次数: 0