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Facilitating side channel analysis by obfuscation for Hardware Trojan detection 为硬件木马检测提供方便的混淆侧信道分析
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-15 DOI: 10.1109/IDT.2015.7396749
Arash Nejat, D. Hély, V. Beroulle
{"title":"Facilitating side channel analysis by obfuscation for Hardware Trojan detection","authors":"Arash Nejat, D. Hély, V. Beroulle","doi":"10.1109/IDT.2015.7396749","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396749","url":null,"abstract":"Integrated Circuit (IC) piracy and malicious alteration, named as Hardware Trojan (HT), are two important threats which may happen in untrusted foundries. Functionality obfuscation has been proposed against IP/IC piracy. Obfuscation can also offer opportunities to defeat HT insertion, because the HT designer cannot understand the functionality of the obfuscated ICs. In addition various HT detection methods have been proposed based on conventional functional or structural tests, and side channel analysis. Conventional functional or structural tests are inefficient if the HT is not completely activated. HT detection by side channel analysis faces Process Variation (PV) and Environment Variation (EV). An HT is detectable if its effect is significant among PV and EV. In this work we propose to use obfuscation methods to facilitate power and path delay analysis based HT detection methods. Since shorter paths have less PV than longer paths; the first approach is to generate shorter paths for nets that only belong to long paths, while the circuit is being obfuscated. The second suggested approach is to increase the proportion of HT dynamic power to the total dynamic power of circuit, while the circuit is being obfuscated. The success of power analysis based HT detection methods is increased by increasing this proportion.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 10 Gbps ADC-based equalizer for serial I/O receiver 用于串行I/O接收器的10gbps adc均衡器
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396733
Khaled A. El-Gammal, Ahmed N. Hassan, S. Ibrahim
{"title":"A 10 Gbps ADC-based equalizer for serial I/O receiver","authors":"Khaled A. El-Gammal, Ahmed N. Hassan, S. Ibrahim","doi":"10.1109/IDT.2015.7396733","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396733","url":null,"abstract":"This paper introduces the system architecture and implementation of a 10Gbps ADC-Based Equalizer for Serial I/O Receiver. The system consists of 2 main building blocks. The first is a 4-channel 4-bit flash analog-to-digital converter with 10 Gbps sampling speed which was implemented using a modified clocking scheme that improves the ADC accuracy and resolution without the need for digital calibration. The ADC achieves a figure of merit of 115 fJ/conversion-step, and was tested for input signals up to 5GHz. The second block is a 2-tap FFE, 3-tap DFE, 10-Gbps digital adaptive equalizer. The equalizer is capable of compensating more than 40 dB of attenuation at Nyquist frequency. The adaptive algorithm used is LMS algorithm using either training sequence mode or blind equalization mode. The system was designed using 65nm CMOS technology.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A proposed methodology to improve UVM-based test generation and coverage closure 改进基于uvm的测试生成和覆盖关闭的建议方法
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396754
Khaled Fathy, K. Salah, R. Guindi
{"title":"A proposed methodology to improve UVM-based test generation and coverage closure","authors":"Khaled Fathy, K. Salah, R. Guindi","doi":"10.1109/IDT.2015.7396754","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396754","url":null,"abstract":"Verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randomly explore the design space to explore corners in depth. Setting up a test case for such designs requires a well-defined stimulus generation methodology. Off-the-shelf scenario libraries and a synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, we define a methodology for creating test scenarios and making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process. We built our methodology as a generic library code to be reused in many designs. A recent memory controller design is used to demonstrate our methodology. The results of applying this methodology on test cases show enhancements on coverage closure and performance.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation 具有失配衰减的低温系数曲率补偿带隙基准
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396734
Mahitab ElAdwy, S. Ibrahim, M. Dessouky
{"title":"A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation","authors":"Mahitab ElAdwy, S. Ibrahim, M. Dessouky","doi":"10.1109/IDT.2015.7396734","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396734","url":null,"abstract":"A high-order curvature-compensated bandgap reference (BGR) with low temperature coefficient (TC) is proposed in this paper. The curvature compensation is maintained through the use of Pplus poly resistor and Nplus poly resistor to achieve temperature-dependent resistor ratios. A T-resistor structure is adopted which enables the BGR to work under low supply voltage or high MOSFET threshold voltage and to reduce the mismatches in transistors and resistors. The design is implemented in 65-nm CMOS technology with a 1.8-V supply. The output reference voltage is 550 mV and shows a TC of 0.22 ppm/°C in a temperature range from -20 °C to 80 °C. A high gain operational amplifier is used that enhances the power supply rejection ratio to -117.8 dB at DC and -75 dB at 1 kHz. The effect of mismatch is 4.3%. The proposed BGR achieves a line regulation of 0.8 mV/V and total power consumption of 20.8 μW.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134549568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A method of LFSR seed generation for hierarchical BIST 一种分层BIST的LFSR种子生成方法
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396747
Kosuke Sawaki, S. Ohtake
{"title":"A method of LFSR seed generation for hierarchical BIST","authors":"Kosuke Sawaki, S. Ohtake","doi":"10.1109/IDT.2015.7396747","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396747","url":null,"abstract":"In built-in self-test (BIST), pseudo-random patterns generated by a linear feedback shift register (LFSR) are applied to a circuit under test as test patterns. Since random pattern resistant faults (RPRFs) exist, reseeding is used to detect them. In general, seeds that when expanded by the LFSR will produce test patterns for detecting RPRFs are used for reseeding. So far, we have proposed a one-pass seed generation method for generating such seeds for scan-based BIST. In this paper, we introduce the concept of the one-pass method into seed generation for hierarchical BIST utilizing register-transfer level (RTL) information. The proposed method can identify untestable faults under the BIST environment and guarantees to generate seeds for detectable faults. In our experiments for several RTL benchmark circuits, we show that seeds generated by the proposed method can reduce test application time for RPRFs of the circuits.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132091072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Toward the interfacing of systemC-AMS models with hardware-emulated platforms systemC-AMS模型与硬件仿真平台的接口研究
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396736
H. Tawfik, M. Safar, Mohamed Abdel Salam, M. El-Kharashi, A. Salem
{"title":"Toward the interfacing of systemC-AMS models with hardware-emulated platforms","authors":"H. Tawfik, M. Safar, Mohamed Abdel Salam, M. El-Kharashi, A. Salem","doi":"10.1109/IDT.2015.7396736","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396736","url":null,"abstract":"Systems on chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components. In some verification environments, SystemC models the digital components and SystemC-AMS extensions can be used to model the analog part. In an emulation environment, the digital components would be probably running on the emulator while the SystemC-AMS components would be running on the associated emulator host machine. In this paper, we propose an approach to interface those digital and analog components. This is challenging because SytemC-AMS is a timed environment with a time wheel completely decoupled from emulation time. We also propose a transaction packing technique that will minimize the communication overhead introduced due to frequent exchange of data between the components running on the emulator and the components running on the host machine. Finally, we describe a case study that illustrates the feasibility of the proposed interfacing approach.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127463448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Aging and leakage tradeoff in VLSI circuits VLSI电路中的老化与泄漏权衡
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396745
Hao Luo, M. Nourani
{"title":"Aging and leakage tradeoff in VLSI circuits","authors":"Hao Luo, M. Nourani","doi":"10.1109/IDT.2015.7396745","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396745","url":null,"abstract":"Bias Temperature Instability (BTI) has become a serious reliability issue for digital circuits. BTI-induced transistor aging degrades transistor performance over time and may eventually induce circuit failure due to timing variations. The leakage power dissipation is another concern as technology scales. While multiple Vth and pin reordering are know as to reduce power leakage, both methods would affect transistor aging. In this paper, we propose an integer linear programming (ILP) based method to optimize VLSI circuits by considering aging-leakage tradeoff. The experimental results show up to 84% leakage power saving within the delay degradation constraint.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130732766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
BTI analysis of SRAM write driver SRAM写驱动的BTI分析
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396744
I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, F. Catthoor
{"title":"BTI analysis of SRAM write driver","authors":"I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, F. Catthoor","doi":"10.1109/IDT.2015.7396744","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396744","url":null,"abstract":"Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122298347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A novel wavelet-based method for TSV modeling 一种新的基于小波的TSV建模方法
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396751
K. Salah
{"title":"A novel wavelet-based method for TSV modeling","authors":"K. Salah","doi":"10.1109/IDT.2015.7396751","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396751","url":null,"abstract":"This paper presents a new computational mathematical model based on Haar-wavelet transform to investigate the TSV and extract its parasitics. A wavelet is used to accelerate the convergence rate of the iterative solver as the conventional basis yields a full matrix, but the wavelet expansion results in a nearly diagonal or nearly block-diagonal sparse matrix. Moreover, the wavelets can be used to reveal important aspects that cannot be noticed by conventional methods. The TSV has been analyzed using conventional moment method in conjunction with wavelet. The results show good agreement with the results obtained in literature. This work is a first step toward applying Wavelets in modeling TSVs to reduce the simulation time significantly, while maintaining the same degree of accuracy presented by the conventional modeling technique. Wavelets present a framework for accelerating the solution of electromagnetic problems.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121754608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation NRTBox:一个Matlab Simulink工具箱，用于使用离散事件仿真进行NoC开关性能评估和早期架构探索
2015 10th International Design & Test Symposium (IDT) Pub Date : 2015-12-01 DOI: 10.1109/IDT.2015.7396743
Samir Ben Abid, Nejib Mediouni, O. Kallel, S. Hasnaoui
{"title":"NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation","authors":"Samir Ben Abid, Nejib Mediouni, O. Kallel, S. Hasnaoui","doi":"10.1109/IDT.2015.7396743","DOIUrl":"https://doi.org/10.1109/IDT.2015.7396743","url":null,"abstract":"Early design space exploration has been shown to be an important factor in reducing the development time for Network on Chips. In this paper, we present a Matlab toolbox aimed at the early-stage design space exploration for NoC router design, the router founding element of a NoC. The toolbox is based on the discrete event simulation engine SimEvents. The presented toolbox can be used to graphically design routers and measure their performances (throughput, latency, etc.) A proof of concept design of a 3D NoC router using Toolbox is, also, presented.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115535782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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