Aging and leakage tradeoff in VLSI circuits

Abstract

Bias Temperature Instability (BTI) has become a serious reliability issue for digital circuits. BTI-induced transistor aging degrades transistor performance over time and may eventually induce circuit failure due to timing variations. The leakage power dissipation is another concern as technology scales. While multiple Vth and pin reordering are know as to reduce power leakage, both methods would affect transistor aging. In this paper, we propose an integer linear programming (ILP) based method to optimize VLSI circuits by considering aging-leakage tradeoff. The experimental results show up to 84% leakage power saving within the delay degradation constraint.