{"title":"具有失配衰减的低温系数曲率补偿带隙基准","authors":"Mahitab ElAdwy, S. Ibrahim, M. Dessouky","doi":"10.1109/IDT.2015.7396734","DOIUrl":null,"url":null,"abstract":"A high-order curvature-compensated bandgap reference (BGR) with low temperature coefficient (TC) is proposed in this paper. The curvature compensation is maintained through the use of Pplus poly resistor and Nplus poly resistor to achieve temperature-dependent resistor ratios. A T-resistor structure is adopted which enables the BGR to work under low supply voltage or high MOSFET threshold voltage and to reduce the mismatches in transistors and resistors. The design is implemented in 65-nm CMOS technology with a 1.8-V supply. The output reference voltage is 550 mV and shows a TC of 0.22 ppm/°C in a temperature range from -20 °C to 80 °C. A high gain operational amplifier is used that enhances the power supply rejection ratio to -117.8 dB at DC and -75 dB at 1 kHz. The effect of mismatch is 4.3%. The proposed BGR achieves a line regulation of 0.8 mV/V and total power consumption of 20.8 μW.","PeriodicalId":321810,"journal":{"name":"2015 10th International Design & Test Symposium (IDT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation\",\"authors\":\"Mahitab ElAdwy, S. Ibrahim, M. Dessouky\",\"doi\":\"10.1109/IDT.2015.7396734\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-order curvature-compensated bandgap reference (BGR) with low temperature coefficient (TC) is proposed in this paper. The curvature compensation is maintained through the use of Pplus poly resistor and Nplus poly resistor to achieve temperature-dependent resistor ratios. A T-resistor structure is adopted which enables the BGR to work under low supply voltage or high MOSFET threshold voltage and to reduce the mismatches in transistors and resistors. The design is implemented in 65-nm CMOS technology with a 1.8-V supply. The output reference voltage is 550 mV and shows a TC of 0.22 ppm/°C in a temperature range from -20 °C to 80 °C. A high gain operational amplifier is used that enhances the power supply rejection ratio to -117.8 dB at DC and -75 dB at 1 kHz. The effect of mismatch is 4.3%. The proposed BGR achieves a line regulation of 0.8 mV/V and total power consumption of 20.8 μW.\",\"PeriodicalId\":321810,\"journal\":{\"name\":\"2015 10th International Design & Test Symposium (IDT)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 10th International Design & Test Symposium (IDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDT.2015.7396734\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 10th International Design & Test Symposium (IDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2015.7396734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation
A high-order curvature-compensated bandgap reference (BGR) with low temperature coefficient (TC) is proposed in this paper. The curvature compensation is maintained through the use of Pplus poly resistor and Nplus poly resistor to achieve temperature-dependent resistor ratios. A T-resistor structure is adopted which enables the BGR to work under low supply voltage or high MOSFET threshold voltage and to reduce the mismatches in transistors and resistors. The design is implemented in 65-nm CMOS technology with a 1.8-V supply. The output reference voltage is 550 mV and shows a TC of 0.22 ppm/°C in a temperature range from -20 °C to 80 °C. A high gain operational amplifier is used that enhances the power supply rejection ratio to -117.8 dB at DC and -75 dB at 1 kHz. The effect of mismatch is 4.3%. The proposed BGR achieves a line regulation of 0.8 mV/V and total power consumption of 20.8 μW.