FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem

This paper presents the Hardware/Software (HW/SW) implementation of Scalar Multiplication (SM) for Elliptic Curve Cryptosystem (ECC) over prime field Fp At low level of abstraction, the SM execution is based on the Modular Addition Subtraction (MAS) and the Modular Multiplication (MM) operations. In this work, we propose the implementation of the SM as a Programmable System on Chip (PSoC), using the MicroBlaze soft processor core of Xilinx. In the proposed embedded system, the control of the SM algorithm is executed by the embedded processor, while the MASs and the MMs are computed within specific hardware. The results show that the execution time of 160-bits and 256-bits SM are respectively about 700ms and 1354ms. The architecture requires only 1960 occupied slices.