Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems最新文献_第2页

A fast pipelined complex multiplier: the fault tolerance issues 一个快速流水线复杂乘法器:容错问题

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224347

L. Breveglieri, V. Piuri, D. Sciuto

引用次数: 1

Analysis of defect maps of large area VLSI ICs 大面积VLSI集成电路缺陷图分析

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224348

I. Koren, Z. Koren, C. Stapper

引用次数: 3

On fault probabilities and yield models for analog VLSI neural networks 模拟VLSI神经网络的故障概率和良率模型

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224358

P. Furth, A. Andreou

引用次数: 4

Concurrent error detection in ALUs by recomputing with rotated operands 用旋转操作数重计算alu并发错误检测

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224374

J. Li, E. Swartzlander

{"title":"Concurrent error detection in ALUs by recomputing with rotated operands","authors":"J. Li, E. Swartzlander","doi":"10.1109/DFTVS.1992.224374","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224374","url":null,"abstract":"Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used to make RERO feasible. This control hardware may add additional faults which are different from the bit-slice faults in the ALU. In this approach, by adding only one spare bit slice in the arithmetic logic unit, RERO is possible for error detection of logical and arithmetic operations in either ripple carry adders and carry lookahead adders without any additional hardware control unit. Proof will be given that RERO-k can detect (k mod n) consecutive errors in logical operations and (k mod (n+1)-1) consecutive errors in arithmetic operations, where n is the length of the original arithmetic logic unit. This demonstrates that RERO preserves all the error detection features of RESO. With less hardware, time redundancy and more flexibility for error detection, the approach makes RERO more appropriate for VLSI designs.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132945335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Optical inspection of wafers using large-area defect detection and sampling 采用大面积缺陷检测和取样的晶圆光学检测

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224365

S. Riley

引用次数: 7

Practical application of automated fault diagnosis at the chip and board levels 在芯片和板级自动故障诊断的实际应用

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224345

M. Maccanelli, A. Halliday, B. Bell, D. Steiss, K. Butler

{"title":"Practical application of automated fault diagnosis at the chip and board levels","authors":"M. Maccanelli, A. Halliday, B. Bell, D. Steiss, K. Butler","doi":"10.1109/DFTVS.1992.224345","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224345","url":null,"abstract":"As the sizes of electronic products grow larger, the process of diagnosing failed components becomes increasingly complex. The problem is compounded by the fact that there exists no unified system with which to diagnose problems at all levels of the product design-integrated circuit (IC), printed circuit board (PCB), and system. This paper presents the results of an industrial experiment with techniques for automating the diagnosis process. The authors have developed a prototype automated fault diagnosis (AFD) system which can input a fault dictionary from either of two different commercial ATPG systems along with results from test pattern application and produce a list of candidate defect sites within a given circuit. The authors ran the prototype against simulated single and multiple stuck-at faults in a portion of a commercial floating point unit and at the PCB level using a special test PCB. Results have been encouraging in that the authors have obtained fairly accurate diagnoses with relatively low coverage stuck-at fault sets and in the presence of simulated non-classical defects. It is possible to produce a uniform methodology for AFD at the IC and PCB levels.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123883176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design rule centring for row redundant content addressable memories 为行冗余内容可寻址存储器设计规则中心

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224353

W.B. Noghani, I. Jalowiecki

引用次数: 1

Efficient bi-level reconfiguration algorithms for fault tolerant arrays 容错阵列的高效双级重构算法

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224367

R. Libeskind-Hadas, N. Shrivastava, R. Melhem, C.L. Liu

{"title":"Efficient bi-level reconfiguration algorithms for fault tolerant arrays","authors":"R. Libeskind-Hadas, N. Shrivastava, R. Melhem, C.L. Liu","doi":"10.1109/DFTVS.1992.224367","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224367","url":null,"abstract":"Considers the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable. Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. It is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that this algorithm is very effective.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115943649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High-speed parallel input-output bit-sliced fault-tolerant convolvers 高速并行输入输出位片容错卷积器

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224346

L. Dadda, M. Sami

引用次数: 6

Lessons learnt from designing a wafer scale 2D array 设计晶圆级二维阵列的经验教训

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224377

A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe

引用次数: 2