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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems最新文献

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Improved layer assignment for packaging multichip modules 改进了封装多芯片模块的层分配
Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224343
C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia
{"title":"Improved layer assignment for packaging multichip modules","authors":"C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia","doi":"10.1109/DFTVS.1992.224343","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224343","url":null,"abstract":"The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lower bound.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"51 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125561032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PLA decomposition to reduce the cost of concurrent checking 分解聚乳酸，减少并发检查的成本
Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224375
D. Wessels, J. Muzio
{"title":"PLA decomposition to reduce the cost of concurrent checking","authors":"D. Wessels, J. Muzio","doi":"10.1109/DFTVS.1992.224375","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224375","url":null,"abstract":"Proposes a combination of PLA decomposition and unidirectional error detecting techniques which permits concurrent testing for all single faults in a circuit (both in the decomposed modules and on the interconnection lines), for a lower area overhead cost than is normally associated with unidirectional error detecting codes.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect level estimation for digital ICs 数字集成电路缺陷水平估计
Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224363
J. Sousa, João Paulo Teixeira
{"title":"Defect level estimation for digital ICs","authors":"J. Sousa, João Paulo Teixeira","doi":"10.1109/DFTVS.1992.224363","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224363","url":null,"abstract":"Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116651171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum 基于扩展重排汉明校验和的高效算法容错设计
Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI: 10.1109/DFTVS.1992.224351
C. Oh, H. Youn, V. K. Raj
{"title":"An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum","authors":"C. Oh, H. Youn, V. K. Raj","doi":"10.1109/DFTVS.1992.224351","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224351","url":null,"abstract":"Fault tolerance has been an important issue for systems involving intensive computations using a large number of processing elements. To effectively tolerate operation time faults in the systems, algorithm-based fault tolerance designs have been developed. Extended rearranged Hamming checksum scheme is proposed as an algorithm-based fault tolerance design. It is based on the rearranged Hamming checksum code with newly introduced negative elements in the checksum matrix. The overflow and round-off error probability of the scheme are greatly reduced compared to earlier designs, while both time latency and hardware overheads are small. Two important matrix computations are selected to show how the scheme works. Performance of the proposed design is evaluated and compared with those of existing schemes through computer simulation.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128950680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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