Defect level estimation for digital ICs

Abstract

Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach.<>