高速并行输入输出位片容错卷积器

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224346

L. Dadda, M. Sami

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引用次数: 6

摘要

提出了一种高采样率的卷积算子族，该算子族的特征是由一比特样本和可在相同的比特切片中分解的模块化规则结构组成。采样以并行或斜向形式表示，整个电路为顺序电路，其组合部分为全加法器阵列，保证了高采样率。还讨论了容错规定。

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High-speed parallel input-output bit-sliced fault-tolerant convolvers

A family of convolvers for high sample rate is proposed, based on the composition of subconvolvers characterized by one bit samples and by modular, regular structures decomposable in identical bit-slices. Samples are represented in parallel or in skew form and the whole circuit is a sequential circuit whose combinatorial part is an array of full adders, assuring a high sampling rate. Fault tolerance provisions are also discussed.<>

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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