Lessons learnt from designing a wafer scale 2D array

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224377

A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe

引用次数: 2

Abstract

Describes how defect tolerance is achieved for a wafer scale architecture that has been implemented on silicon. It gives an overview of a long-term research effort and describes software methods and tools as well as hardware switching devices used to create a defect free 2D array at end of manufacturing. This wafer scale architecture is called ELSA (European Large SIMD Array) and has been studied within an ESPRIT project on wafer scale integration.<>

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设计晶圆级二维阵列的经验教训

描述在硅上实现的晶圆级架构如何实现缺陷容限。它概述了长期的研究工作，并描述了用于在制造结束时创建无缺陷2D阵列的软件方法和工具以及硬件开关设备。这种晶圆规模架构被称为ELSA(欧洲大型SIMD阵列)，并已在ESPRIT晶圆规模集成项目中进行了研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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