On fault probabilities and yield models for analog VLSI neural networks

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224358

P. Furth, A. Andreou

引用次数: 4

Abstract

Investigates the estimation of fault probabilities and yield for analog VLSI implementations of neural computation. The analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. The work improves on the framework suggested recently by Feltham and Maly (1991) and is also applicable to analog or mixed analog/digital VLSI systems.<>

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模拟VLSI神经网络的故障概率和良率模型

研究了神经计算的模拟VLSI实现的故障概率和良率估计。分析仅限于可以直接映射到硅作为真正的分布式并行处理系统的结构。这项工作改进了Feltham和Maly(1991)最近提出的框架，也适用于模拟或混合模拟/数字VLSI系统

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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