2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)最新文献

{"title":"Interfacial reactions between Sn-3.8 Ag-0.7Cu solder and Ni-W alloy films","authors":"C. S. Chew, A. Haseeb, M. Johan","doi":"10.1109/IEMT.2012.6521744","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521744","url":null,"abstract":"In this study, interfacial reactions between Ni-W alloy films and Sn-3.8Ag-0.7Cu solder have been investigated. Ni-W alloys films with tungsten content in the range of 5.0-18.0 at.% was prepared on copper substrate by electrodeposition in ammonia citrate bath. Solder joints were prepared on the Ni-W coated substrate at a reflow temperature of 250°C. The solder joint interface was investigated by cross-sectional scanning electron microscopy, energy dispersive X-ray spectroscopy and electron back scatter diffraction. It has been observed that a (Cu, Ni)6Sn5 layer formed on the Ni-W alloy film after reflow. The thickness of the (Cu, Ni)6Sn5 layer was found to decrease with the increase of tungsten content in the Ni-W film. An additional layer with a bright appearance was also found to form below the (Cu, Ni)6Sn5 layer. The bright layer was identified to be a ternary phase containing Sn, Cu, W and Ni. The bright layer is found to be amorphous and is suggested to have formed through solid state amorphization caused by anomalously fast diffusion of Sn into Ni-W film.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123015675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bond stitch on ball for bare copper wire","authors":"Tan Kai Chat, Liong Jin Yoong","doi":"10.1109/IEMT.2012.6521807","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521807","url":null,"abstract":"The integration of multiple functions IC into single package including MCM package, 3D stacking, system in package had became a trend in recent year. In addition, demand of thin packages is rapidly gaining momentum with the emerging of advance handheld consumer products. All of these integrations and developments need BSOB bonding for interconnection purpose. Cu wire with lower cost, better reliability and electrical performance is favored in packaging material selection but BSOB in Cu wire is a rare case and inherent its challenges during implementation. For success Cu BSOB bond, bond pad structure design must be robust enough to withstand two time thermosonic impact, perfect integration between bump & stitch must be in place and ball bond had to be firmly bonded on Ag/PPF surface. Success of characterization will be lifmited if these few factors are not considered. In this study, we will discuss challenges encountered during bare Cu BSOB characterization i.e Cu bump formation stability and consistency, interaction of oxidized bump with 2nd bond stitch on Cu oxide surface by mean of stitch pull strength, cross-section analysis with varies bump staging time, BOAC bond pad structure robustness test without failure at extreme condition, and ball bond integrity on uPPF surface. Complete understanding of multiple interacting factors will promise a robust bonding condition with long term stability.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124952263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intermetallic evolution between Sn-3.5Ag-1.0Cu-xZn lead free solder and copper substrate under long time thermal aging (x: 0, 0.1, 0.4, 0.7)","authors":"I. Yahya, N. A. A. Ghani, M. M. Salleh, H. A. Hamid, Z. Ahmad, R. Mayappan","doi":"10.1109/IEMT.2012.6521765","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521765","url":null,"abstract":"Due to environmental concern regarding toxicity of lead-based solder, the lead-free solders were introduced as a replacing solder in microelectronics devices technology. In this study, the effects of 0.1, 0.4 and 0.7 wt% Zn additions on the intermetallic formation and thickness of Sn-3.5Ag-1.0Cu solder on Cu substrate after long time aging were investigated. The X-Ray Diffraction (XRD) analysis shown that there were Cu6Sn5, Cu3Sn, β-Sn, CuZn and Ag3Sn phase formed after sintering process. The morphology of the intermetallic was observed under Scanning Electron Microscope (SEM) and the elemental distribution was confirmed by Energy Dispersive X-ray (EDX). The intermetallic thickness increases as the aging temperature increases while the addition of zinc into the system has suppressed the intermetallic formation.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pd coated Cu wire bond on XoAA material in LQFP package","authors":"W. Yong, J. Teo, G. Lee, Tan Kian Heong, A. Swee","doi":"10.1109/IEMT.2012.6521840","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521840","url":null,"abstract":"Pd coated wire is increasely being used as a substitute for bare Cu wire. Being a noble metal, Pd coated wire has high resistance to oxidation enabling longer shelf life. Its chemical properties also exhibit better second bond-ability on micro PPF lead frame enabling simple bond process translating to high throughput and yield. It has higher stiffness which is able to minimize the wire sweep especially for LQFP, as well as thermo-mechnical robustness. However, there are a few challenges to be overcomed before the bonding process can be released. Basically, Pd will diffuse non-uniformly into FAB after EFO sparking. The formation of Pd-Cu alloys will increase FAB hardness resulting in higher risk of oxide crack issue. Technically, due to its physical properties, Pd coated wire will produce higher bonding impact on the bond pad in order to achieve stable and reliable 1 st bond process. Conversely, this approach is not feasible for XoAA material. A new 1 st bonding process has to be developed that can produce a stable bond yet able to meet all buy off requirements. This paper will show the study of Pd coated wire interaction with pad metallization of NiP/Pd/ Au on XoAA material. In the 1 st bond process technology development, the effect of capillary on pad structure are examined. The traditional capillary design appears to be detrimental to XoAA material. A special capillary design was introduced that incorporated a different bond mechanism with the consideration of wire properties and pad structure. An extensive Design of Experiment (DOE) is carried out to define a robust process window. New analysis method by using optical profiling was also introduced for quick and reliable assessment for pad deformation. Bond interface was also validated. Transmission Electron Microscopy (TEM) with EDX line scan analysis showed the presence of Cu-Pd at the bond interface. This study also established two criterias to control oxide crack issue. This process technology is proven and able to meet automotive requirement. In short, the requirements to achieve stable bondability and reliability has been developed in this study.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust power package development with mechanical simulation and reliability validation","authors":"Xueren Zhang, K. Goh, Yiyi Ma, W. Wong","doi":"10.1109/IEMT.2012.6521771","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521771","url":null,"abstract":"Thermo-mechanical reliability is one of the major concerns for electronic packages, especially for power packages operating in extremely harsh environment. As the trends towards high density and function integration, advanced power device becomes more sensitive to environmental stress. Comprehensive study is needed from design, process to test towards robust power package with high reliability. In this paper, we will demonstrate the successful application of simulation in the development of a series of robust leaded power packages. Firstly, finite element analysis(FEA) has been carried out to understand die stress behavior inside the package during assembly and reliability tests, i.e. from die attach, post mold cure, reflow to thermal cycling etc. Then DOE matrix is run to obtain the critical responses to different factors, which leads to guidelines on package design and material selection. A series of robust power packages have been developed with optimized package geometry and bill of materials.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131352642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder ball robustness study on polymer core solder balls for BGA packages","authors":"Y. B. Kar, Tan Cai Hui, A. Agileswari, C. Lo","doi":"10.1109/IEMT.2012.6521760","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521760","url":null,"abstract":"Restriction of Hazardous Substance (RoHS) Regulation came into effect in 2006 due to the hazardous effects of lead to human's health and toxicity for environment. As such, the leaded solder ball was replaced by lead-free solder ball which is now widely used in semiconductor industries. However, there was a concern on the robustness of lead-free solder ball especially on drop ball issues when compared to lead solder ball, especially when subjected to reliability stress tests. The polymer core solder ball was invented to solve the drop ball issue. Polymer core solder ball with an additional polymer core inside the solder functions as a stress buffer to dissipate stress better compared to the current conventional lead-free solder ball. However, a new problem arises which is the formation of Kirkendall voids in between the Copper (Cu) and solder interface which results in poor reliability performance. This formation of voids could be due to the faster diffusion from Cu to Tin (Sn) than Sn to Cu. Therefore, an additional Nickel (Ni) layer is coated on top of Cu to overcome this problem. The function of Ni is to limit / reduce the diffusion from Cu to Sn thus preventing the formation of Kirkendall voids. This enhances the robustness of the solder ball joint. The solder ball shear strength test and tray drop test were conducted in this research study under different reliability stress conditions such as temperature cycle (TC) and high temperature storage (HTS) stress to verify the robustness and the reliability of the polymer core solder balls. The solder ball shear strength experiment was conducted via Dage 4000 series bond tester and drop reliability test was carried out via the tray drop test. It is observed that the shear strength for polymer core solder ball without Ni coating layer decreased in TC and HTS stress condition and the tray drop test reliability is the worst in HTS 1008 hours. This is due to the excessive formation of Kirkendall voids resulting from the faster diffusion rate from Cu to Sn than Sn to Cu. From this research study, it can be concluded that the polymer core solder ball with an additional of Ni coating layer gives higher joint strength and better drop reliability performance compared to the polymer core solder ball without additional Ni coating layer.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cavity packages for volume MEMS applications","authors":"A. Evans","doi":"10.1109/IEMT.2012.6521801","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521801","url":null,"abstract":"","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132141351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced fan-out WLP for high power device packaging","authors":"Yonggang Jin, J. Teysseyre, A. R. Y. Liu, G. Goh, Yiyi Ma, S. Yoon","doi":"10.1109/IEMT.2012.6521784","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521784","url":null,"abstract":"With the advancement of fan-out embedded wafer level packaging technology (eWLB), it is more and more promising compared with fan-in WLP, because it can offers great feasibility and flexibility for more I/Os, multi-chips, and system integration. But there are some restrictions in possible applications for Fan-In WLP or Fan-out WLP since global chip trends tend toward smaller chip areas with an increasing number of interconnects and better thermal performance. Fan-out wafer level packaging has been developed in the last past 5 years. Advantages of Fan-out WLP are included smaller footprint; thinner package thickness with thinning of molded wafer. For further smaller profile and smaller package size, QFN-like package format is studied and developed. eWLL(embedded wafer level LGA) is developed for further thinner profile and smaller form without solder ball. It can be significant advantage of low profile and miniaturized applications. However some challenge is foreseen with eWLL, includes thermal performance, eletromigration and reliability for high power application. This paper will focus on simulation study and test data correlation.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131445787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder microstructure and intermetallic interface evaluation between Sn-3.5Ag-1.0Cu-xNi lead free solder under long time thermal aging (x: 0, 0.05, 0.2, 0.5)","authors":"N. A. A. Ghani, I. Yahya, M. M. Salleh, S. Shamsuddin, Z. Ahmad, R. Mayappan","doi":"10.1109/IEMT.2012.6521764","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521764","url":null,"abstract":"Sn-3.5Ag-1.0Cu-xNi (x: 0, 0.05, 0.2, 0.5) solder alloy has been developed to improve properties and microstructure of Sn-3.5Ag-1.0Cu based solder. The composite solder were synthesized via the powder metallurgy route which consist of blending, compacting and sintering process. The sintered solders were characterized for it melting temperature, SEM-EDX analysis was done to confirm the homogeneity of sample element distribution and X-Ray diffraction (XRD) analysis was conducted to see the presents of some phases. XRD analysis of sintered sample showed the presents of Ni3Sn4 and Ni3Sn2 phases. Solders were melted on copper substrate at 250°C for one minute on hot plate and aged at 150°C from 0 to 400 hours. The microstructure of the solder and the growth of IMC formation were studied under Scanning Electron Microscope (SEM) and EDX. The phases formed were studied under SEM-EDX. The SEM results show the presence of Cu6Sn5, Cu3Sn and Ag3Sn intermetallic in the Sn-3.5Ag-1.0Cu solder and Sn-3.5Ag-1.0Cu-xNi solder.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the drop impact performance of IPDTM devices with different process technologies","authors":"Yiyi Ma, K. Goh, Xueren Zhang, W. Goh","doi":"10.1109/IEMT.2012.6521790","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521790","url":null,"abstract":"The associated significant loss with passive devices on silicon substrate is generally believed to be responsible for the presence of low quality factors, making it a poor candidate for the design of efficient output matching networks. STMicroelectronics has addressed this issue by coming up with a low-loss passive technology called IPD™ (Integrated Passive Devices) RLC06 technology, which is a passive process on glass substrate featuring high RF performance and high level of integration with either wire bonded or flip chipped interconnects. In this paper, a 2.8mm×2.8mm WLCSP (Wafer Level Chip Scale Package) was used as test vehicle. The drop impact performance of the test vehicle employing two different RDL (ReDistribution Layer) process technologies was evaluated through finite element modeling. Maximum peeling stress in the regions of interest was extracted and analyzed for comparison. Actual drop test was performed to characterize the drop impact durability of the WLCSP. It is found that the simulation result agrees very well with the experimental observations in terms of failure location and relative drop test robustness of the two structures. However, the small difference in maximum peeling stress may not be able to justify their big difference in drop test reliability. It could be due to the intrinsic limitation of the numerical method adopted as well as to the different failure locations of the two structures, where there may be different material toughness. The validated model was then extended to optimize the design of Al pad and Cu via of the alternative bump pad for the WLSCP package subjected to drop test.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114699726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}