Enhanced fan-out WLP for high power device packaging

Abstract

With the advancement of fan-out embedded wafer level packaging technology (eWLB), it is more and more promising compared with fan-in WLP, because it can offers great feasibility and flexibility for more I/Os, multi-chips, and system integration. But there are some restrictions in possible applications for Fan-In WLP or Fan-out WLP since global chip trends tend toward smaller chip areas with an increasing number of interconnects and better thermal performance. Fan-out wafer level packaging has been developed in the last past 5 years. Advantages of Fan-out WLP are included smaller footprint; thinner package thickness with thinning of molded wafer. For further smaller profile and smaller package size, QFN-like package format is studied and developed. eWLL(embedded wafer level LGA) is developed for further thinner profile and smaller form without solder ball. It can be significant advantage of low profile and miniaturized applications. However some challenge is foreseen with eWLL, includes thermal performance, eletromigration and reliability for high power application. This paper will focus on simulation study and test data correlation.