2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第3页

A temperature compensated CMOS relaxation oscillator for low power applications 温度补偿CMOS弛豫振荡器的低功耗应用

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344442

J. Soldera, M. Berens, A. Olmos

引用次数: 6

A 65nm CMOS 60 GHz class F-E power amplifier for WPAN applications 用于WPAN应用的65nm CMOS 60 GHz级F-E功率放大器

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344451

S. Drean, N. Deltimple, E. Kerhervé, B. Martineau, D. Belot

引用次数: 4

Hardware pipelining of runtime-detected loops 运行时检测循环的硬件流水线

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344443

João Bispo, João MP Cardoso, J. Monteiro

引用次数: 1

On-chip 4to20mA reconfigurable current loop transmitter for smart sensor applications 片上4to20mA可重构电流环变送器，用于智能传感器应用

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344434

Jefferson Daniel de Barros Soldera, Julio Saldana, C. G. Penteado, H. Hernández, R. A. Hernandez, Fernando Chavez Porras, Marcos A. Valerio, Angelica dos Anjos, Paulo H. Trevisan

引用次数: 1

A 50MHz–lGHz wideband low noise amplifier in 130nm CMOS technology 基于130nm CMOS技术的50MHz-lGHz宽带低噪声放大器

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344428

Henrique Luiz Andrade Pimentel, S. Bampi

引用次数: 4

Robust modular Bulk Built-in Current Sensors for detection of transient faults 鲁棒模块化内置电流传感器检测瞬态故障

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344422

F. Sill, R. P. Bastos

引用次数: 15

Yield optimization for low power current controlled current conveyor 小功率电流控制电流输送机成品率优化

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344426

Zia Abbas, M. Yakupov, M. Olivieri, A. Ripp, G. Strube

{"title":"Yield optimization for low power current controlled current conveyor","authors":"Zia Abbas, M. Yakupov, M. Olivieri, A. Ripp, G. Strube","doi":"10.1109/SBCCI.2012.6344426","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344426","url":null,"abstract":"Due to increasing CMOS process variability, optimization for yield has become one of the crucial tasks in Integrated Circuit (IC) design especially in analog IC design. This variability is getting worse with the continuous scaling of device dimensions and therefore degrades the IC fabrication outcome. This paper presents the yield optimization for low power second generation dual output current controlled current conveyor (DOCCCII). Current conveyors (CC) are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net list of given DOCCCII circuit has been simulated in Eldo using 65nm CMOS mixed signal Low-K IMD TSMC process development kit (PDK) with ±0.6V, low-Vt devices with statistical models. All verification, sizing and optimization analysis have been performed using the commercially available WiCkeD toolset from MunEDA at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A very low power area efficient CMOS only bandgap reference 一个非常低的功率面积效率CMOS带隙参考

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344437

Edgar Mauricio Camacho-Galeano, A. Olmos, A. V. Boas

引用次数: 3

Current-mode analog integrated circuit for focal-plane image compression 用于焦平面图像压缩的电流模模拟集成电路

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344438

F. D. V. R. Oliveira, H. L. Haas, J. Gomes, A. Petraglia

{"title":"Current-mode analog integrated circuit for focal-plane image compression","authors":"F. D. V. R. Oliveira, H. L. Haas, J. Gomes, A. Petraglia","doi":"10.1109/SBCCI.2012.6344438","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344438","url":null,"abstract":"The interest in focal-plane processing techniques, by which image processing is carried out at pixel level, has increased since the advent of active pixel sensors in the middle 90's. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 imaging integrated circuit that captures and compresses gray scale images on the focal plane of the image sensors using analog circuits that implement, for every 4 × 4 pixel block, differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS, analog convolutions and A/D conversion. Theoretical details and circuit designs are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. Experimental results and photographs captured by the chip are shown to validate the technique. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/cm are preserved in the decoded images.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130464270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding 新兴HEVC视频编码中自适应环路滤波器的高吞吐量硬件设计

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344446

Fabiane Rediess, L. Agostini, Cassio Cristani, Pargles Dall'Oglio, M. Porto

引用次数: 10