High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding

Abstract

This work presents a high throughput hardware design for the Adaptive Loop Filter (ALF) cores, a new technique proposed by the High Efficiency Video Coding (HEVC), the emerging video coding standard, in order to improve the subjective video quality. The ALF is a part of the In-Loop Filter which also includes the Deblocking Filter (DF) and the Sample Adaptive Offset (SAO). These three filters are responsible to improve the final video quality, reducing the errors that are generated in all encoder steps. The ALF is a diamond-shaped filter and it has three sizes: 5×5, 7×7 and 9×9. This work proposes efficient hardware architectures for the filter cores of these three ALF sizes, with focus on real time processing of high definition videos. The architectures were described in VHDL and synthesized to an Altera FPGA, achieving 204MHz in the worst case, and consequently, reaching a minimum frame rate of 98 HD 1080p (1920×1080) frames per second for and 49 WQXGA (2560×1600) frames per second.