2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes 采用m-of-n码的QDI电路c元降低静态功率的归一协议

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344444

Matheus T. Moreira, R. Guazzelli, Ney Laert Vilar Calazans

{"title":"Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes","authors":"Matheus T. Moreira, R. Guazzelli, Ney Laert Vilar Calazans","doi":"10.1109/SBCCI.2012.6344444","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344444","url":null,"abstract":"The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration by means of asynchronous interfaces and communication architectures, forming a globally asynchronous, locally synchronous (GALS) system. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to delay insensitive (DI) codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This work presents a technique to reduce the static power consumption of asynchronous QDI circuits using any m-of-n code and a four-phase handshake protocol, by proposing the utilization of a non-classical spacer encoding, namely all-1s. The article shows that the use of the traditional all-0s spacers may lead to static power consumption figures that are in some cases more than twice larger than the static power consumed by all-1s spacers in C-elements, the most common device used in asynchronous templates. Experiments demonstrate the new spacer reduces static power consumption without increase in complexity.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116887783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements NSP内核查找器-一种查找和构建非串并联晶体管排列的方法

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344452

V. Possani, F. Marques, L. Rosa, V. Callegaro, A. Reis, R. Ribas

引用次数: 6

A formally verified deadlock-free routing function in a fault-tolerant NoC architecture 在容错NoC架构中正式验证的无死锁路由功能

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344433

Abdulaziz Alhussien, N. Bagherzadeh, Freek Verbeek, B. V. Gastel, J. Schmaltz

{"title":"A formally verified deadlock-free routing function in a fault-tolerant NoC architecture","authors":"Abdulaziz Alhussien, N. Bagherzadeh, Freek Verbeek, B. V. Gastel, J. Schmaltz","doi":"10.1109/SBCCI.2012.6344433","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344433","url":null,"abstract":"A novel fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The routing function guarantees absence of deadlocks and livelocks up to two faulty channels. The routing logic does not require reconfiguration when a fault occurs. The routes themselves are dynamic. Based on the faults in the network, alternative routes are used to reroute packets. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. To ensure deadlock freedom, we have extended a formally verified deadlock detection algorithm to deal with fault tolerant designs. For a 20×20 mesh, we have formally proven deadlock freedom of our design in all of the 2,878,800 configurations in which two channels are faulty. We supply experimental results showing the performance of our architecture.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

FPGA design for real time flaw detection on edges using the LEDges technique 利用LEDges技术实现边缘实时缺陷检测的FPGA设计

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344420

Y. N. Batista, C. Araujo, A. Silva-Filho

引用次数: 0

Memory and communication driven spatio-temporal scheduling on MPSoCs 存储器和通信驱动的mpsoc时空调度

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344423

Z. Bhatti, Narasinga Rao Miniskar, D. Preuveneers, Roel Wuyts, Y. Berbers, F. Catthoor

{"title":"Memory and communication driven spatio-temporal scheduling on MPSoCs","authors":"Z. Bhatti, Narasinga Rao Miniskar, D. Preuveneers, Roel Wuyts, Y. Berbers, F. Catthoor","doi":"10.1109/SBCCI.2012.6344423","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344423","url":null,"abstract":"Scheduling and executing software efficiently on contemporary embedded systems, featuring heterogeneous multi-processors, multiple power modes, complex memory hierarchies and advanced interconnects, is a daunting task. State-of-the-art tools that schedule software tasks to hardware resources face limitations: (1) either they do not take into account the interdependancies among processing, memory and communication constraints (2) or they decouple the problem of spatial assignment from temporal scheduling. As a result existing tools make sub-optimal spatio-temporal scheduling decisions. This paper presents a technique to find globally optimized solutions by co-exploring spatio-temporal schedules for computation, data storage and communication simultaneously, considering the interdependencies between them. Experiments on mapping exploration of an image processing application on a heterogeneous MPSoC platform show that this co-exploration methodology finds schedules that are more energy efficient, when compared to decoupled exploration techniques for the particular application and target platform.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121680459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Topological impact on latency and throughput: 2D versus 3D NoC comparison 拓扑对延迟和吞吐量的影响:2D与3D NoC比较

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344439

Y. Ghidini, T. Webber, E. I. Moreno, Ivan Quadros, R. Fagundes, C. Marcon

{"title":"Topological impact on latency and throughput: 2D versus 3D NoC comparison","authors":"Y. Ghidini, T. Webber, E. I. Moreno, Ivan Quadros, R. Fagundes, C. Marcon","doi":"10.1109/SBCCI.2012.6344439","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344439","url":null,"abstract":"NoC has emerged as as efficient communication infrastructure to fulfill the heavy communication requirements of several applications, which are implemented on MPSoC target architectures. 2D NoCs are natural choices of communication infrastructure for the majority of actual chip fabrication technologies. However, wire delay and power consumption are dramatically increasing even when using this kind of topology. In this sense, 3D NoC emerges as an improvement of 2D NoC aiming to reduce the length and number of global interconnections. This work explores architectural impacts of 2D and 3D NoC topologies on latency, throughput and network occupancy. We show that, in average, 3D topologies minimize 30% the application latency and increase 56% the packets throughput, when compared to 2D topologies. In addition, the paper explores the influence of the buffer length on communication architecture latency and on application latency, highlighting that when applying an appropriate buffer length the application latency in reduced up to 3.4 times for 2D topologies and 2.3 times for 3D topologies.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response 对具有对数压缩响应的活动像素扩展使用伪闪光复位技术

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344425

C. Cruz, Israel L. Marinho, D. Monteiro

引用次数: 3

Hardware and software co-design for the AAC audio decoder AAC音频解码器的软硬件协同设计

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344447

R. C. Sampaio, P. Berger, R. Jacobi

引用次数: 4

A PLL for clock generation with automatic frequency control under TID effects 一个锁相环，用于在TID效应下自动频率控制的时钟生成

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344441

Ricardo Vanni Dallasen, G. Wirth, T. H. Both

引用次数: 1

Application-Specific Network-on-Chip synthesis with topology-aware floorplanning 特定应用的片上网络综合与拓扑感知平面规划

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344421

Bo Huang, Song Chen, Wei Zhong, T. Yoshimura

引用次数: 12