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2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

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Differential mixer with NMOS/PMOS stack at switching stage 在切换阶段带有NMOS/PMOS堆叠的差动混频器
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344440
E. Martins, M. A. Alejandro, Thais V. Fogaca
{"title":"Differential mixer with NMOS/PMOS stack at switching stage","authors":"E. Martins, M. A. Alejandro, Thais V. Fogaca","doi":"10.1109/SBCCI.2012.6344440","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344440","url":null,"abstract":"This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115586848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DPA insensitive voltage regulator for contact smart cards 用于接触式智能卡的DPA不敏感电压调节器
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344432
H. Hernández, Jonathan B. Scott, W. Noije
{"title":"DPA insensitive voltage regulator for contact smart cards","authors":"H. Hernández, Jonathan B. Scott, W. Noije","doi":"10.1109/SBCCI.2012.6344432","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344432","url":null,"abstract":"An on-chip voltage regulator for contact smart cards in CMOS technology is presented. The proposed regulator protects the supplied system against power analysis attacks using a charge pump architecture to eliminate the power consumption correlation. It generates a 1.55V output from 1.65V to 5.5V input voltage. The circuit has been sized to handle a 50mA load current step with less than 250mV of voltage ripple without external capacitors. Thus, it can be applied in A, B and C classes of smart cards. The presented circuit was designed in a 0.18μm CMOS technology. The core occupies an area of about 0.15mm2, without Pads.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture 基于pragma的在粗粒度可重构体系结构上映射MATLAB应用程序的方法
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-08-01 DOI: 10.1109/SBCCI.2012.6344445
Omer Malik, A. Hemani
{"title":"A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture","authors":"Omer Malik, A. Hemani","doi":"10.1109/SBCCI.2012.6344445","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344445","url":null,"abstract":"This paper describes a tool that maps DSP functions written in MATLAB on a coarse grained reconfigurable platform with the help of pragmas. Pragmas are architectural hint directives that constraints the design implementation in terms of allocation/binding and explore specific features of platform. The pragmas are symbolic and parametric to make DSP functions generic in terms of the dimension. By sweeping these parameters, the tool can generate solutions of different dimension and varying degrees of parallelism from the same algorithmic level code. The tool performs scheduling, synchronization, control and interconnect generation for each such solution. This enables the pragma annotated functions to serve as generic library elements in a system level synthesis framework that sweeps through the parameters to select a function implementation of right size and optimal parallelism, thus enabling efficient system level design space exploration. In this paper, we describe these pragmas, their syntax, semantics and richly illustrate their usage with examples.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Partitioning-based wirelength estimation technique for Y-routing 基于分区的y路由长度估计技术
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-08-01 DOI: 10.1109/SBCCI.2012.6344436
T. Samanta, H. Rahaman, P. Dasgupta
{"title":"Partitioning-based wirelength estimation technique for Y-routing","authors":"T. Samanta, H. Rahaman, P. Dasgupta","doi":"10.1109/SBCCI.2012.6344436","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344436","url":null,"abstract":"Accurate wirelength estimation is desirable for VLSI circuit design. However, todays increasing design complexity incorporates greater complexity and hence requires a prior estimate of wirelength without performing exact routing. In this paper, we consider Y -routing, and propose a partitioning-based wirelength estimation scheme for multi-terminal nets. We try to find an optimum partition size of a multi-terminal net, and introduce a correction factor to accommodate wirelength variation for geometrical distribution of pin terminals on a layout. Our proposed method is simple and elegant, and yields reasonable solutions in little time. Experimental results with technology dependent benchmarks, and several industry test cases are encouraging.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117300855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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