Partitioning-based wirelength estimation technique for Y-routing

Abstract

Accurate wirelength estimation is desirable for VLSI circuit design. However, todays increasing design complexity incorporates greater complexity and hence requires a prior estimate of wirelength without performing exact routing. In this paper, we consider Y -routing, and propose a partitioning-based wirelength estimation scheme for multi-terminal nets. We try to find an optimum partition size of a multi-terminal net, and introduce a correction factor to accommodate wirelength variation for geometrical distribution of pin terminals on a layout. Our proposed method is simple and elegant, and yields reasonable solutions in little time. Experimental results with technology dependent benchmarks, and several industry test cases are encouraging.