{"title":"DPA insensitive voltage regulator for contact smart cards","authors":"H. Hernández, Jonathan B. Scott, W. Noije","doi":"10.1109/SBCCI.2012.6344432","DOIUrl":null,"url":null,"abstract":"An on-chip voltage regulator for contact smart cards in CMOS technology is presented. The proposed regulator protects the supplied system against power analysis attacks using a charge pump architecture to eliminate the power consumption correlation. It generates a 1.55V output from 1.65V to 5.5V input voltage. The circuit has been sized to handle a 50mA load current step with less than 250mV of voltage ripple without external capacitors. Thus, it can be applied in A, B and C classes of smart cards. The presented circuit was designed in a 0.18μm CMOS technology. The core occupies an area of about 0.15mm2, without Pads.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.2012.6344432","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An on-chip voltage regulator for contact smart cards in CMOS technology is presented. The proposed regulator protects the supplied system against power analysis attacks using a charge pump architecture to eliminate the power consumption correlation. It generates a 1.55V output from 1.65V to 5.5V input voltage. The circuit has been sized to handle a 50mA load current step with less than 250mV of voltage ripple without external capacitors. Thus, it can be applied in A, B and C classes of smart cards. The presented circuit was designed in a 0.18μm CMOS technology. The core occupies an area of about 0.15mm2, without Pads.