一个锁相环,用于在TID效应下自动频率控制的时钟生成

Ricardo Vanni Dallasen, G. Wirth, T. H. Both
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引用次数: 1

摘要

提出了一种带总电离剂量(TID)衰减检测器的锁相环时钟生成方案。在锁相环电路外部,当由于TID效应导致的衰减达到某个预定义的阈值时,电路降低时钟频率输出。为了补偿由总剂量效应(TID)引起的增加的延迟,系统增加时钟周期以避免时间冲突,增加芯片寿命。采用0.35μm CMOS工艺设计了该电路,并用HSPICE工具进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A PLL for clock generation with automatic frequency control under TID effects
This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.
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