{"title":"一个锁相环,用于在TID效应下自动频率控制的时钟生成","authors":"Ricardo Vanni Dallasen, G. Wirth, T. H. Both","doi":"10.1109/SBCCI.2012.6344441","DOIUrl":null,"url":null,"abstract":"This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A PLL for clock generation with automatic frequency control under TID effects\",\"authors\":\"Ricardo Vanni Dallasen, G. Wirth, T. H. Both\",\"doi\":\"10.1109/SBCCI.2012.6344441\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.\",\"PeriodicalId\":311528,\"journal\":{\"name\":\"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBCCI.2012.6344441\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.2012.6344441","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A PLL for clock generation with automatic frequency control under TID effects
This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.