2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

A low complexity lossless data compressor IP-core for satellite images 用于卫星图像的低复杂度无损数据压缩ip核

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344431

Y. G. G. D. Costa, José Antônio Gomes de Lima, Guilherme Navarro

{"title":"A low complexity lossless data compressor IP-core for satellite images","authors":"Y. G. G. D. Costa, José Antônio Gomes de Lima, Guilherme Navarro","doi":"10.1109/SBCCI.2012.6344431","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344431","url":null,"abstract":"As the technology advances, space imaging systems use equipment of increasing resolutions. Hence, it is necessary to ensure that this great quantity of data arrives at its destination reliably. Among some variables involved, data compression plays an important role to accomplish this requirement. In this context, this paper proposes a digital hardware approach of a low complexity satellite image lossless compressor based on prediction and Golomb-Rice coding, which has achieved excellent results considering hardware and compression performance. In order to validate and analyze the compressor, a functional verification and FPGA prototyping methodology were followed. Given an image set from Brazilian's National Institute for Space Research (INPE, in Portuguese acronyms), its results on FPGA show that this compressor achieves compression ratio around 3.4, comparable value to related works in this area, and throughput of 28 MPixel/s (224 Mbit/s). Taking advantage of images nature, its compression can be parallelized through simultaneous multi-cores compressors. For example, using 5 cores, this work is able to compress those images in a rate of 142 MPixel/s (1.1 Gbit/s). All these features make it useful and effective as a current remote sensing imaging system.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127844328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power consumption reduction in MPSoCs through DFS 通过DFS降低mpsoc的功耗

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344429

T. Rosa, Vivian Larrea, Ney Laert Vilar Calazans, F. Moraes

{"title":"Power consumption reduction in MPSoCs through DFS","authors":"T. Rosa, Vivian Larrea, Ney Laert Vilar Calazans, F. Moraes","doi":"10.1109/SBCCI.2012.6344429","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344429","url":null,"abstract":"The use of power management techniques is mandatory in embedded devices, which must provide high performance with low energy consumption. Due to the high variability present in the applications workload executed by these devices, this management should be executed dynamically. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved to be useful in several scenarios to save energy. Nonetheless, due to technology scaling that limits the voltage variation and slow response of the DVFS schemes, the use of such technique may become inadequate. As alternative, the use of dynamic frequency scaling (DFS) may provide a good trade-off between power savings and power overhead. This paper proposes a distributed DFS scheme for NoC-based MPSoCs. Both NoC and PEs have an individual controlling scheme. The DFS scheme for PEs takes into account its computation and communication load to dynamically change the operating frequency. In the NoC, the DFS controller uses packet information to decide the router operating frequency. Real and synthetic applications were used to evaluate the proposed scheme. Results show that the number of executed instructions is reduced up to 41%, with an execution time overhead up to 18%. The power dissipation is reduced in PEs up to 26% and in the NoC up to 76%.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121295890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector 用于DSP工业应用的FPGA设计方法-三相正序检测器的案例研究

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344430

P. S. B. Nascimento, F. Neves, H. Souza, M. A. O. Domingues

{"title":"FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector","authors":"P. S. B. Nascimento, F. Neves, H. Souza, M. A. O. Domingues","doi":"10.1109/SBCCI.2012.6344430","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344430","url":null,"abstract":"Very important fields for utilization of FPGA technology are industrial applications such as power converters, renewable energy systems, uninterruptible power supplies, active power filters, dynamic voltage restorers and power systems protection. Many of these applications require the detection of three-phase signals characteristics. Generally, these techniques are implemented in DSP devices, with the execution time limited by sample rates of input signals. FPGA implementation results in several advantages. In this paper, an FPGA design flow for industrial digital signal processing is proposed. The first contribution is a metric for comparison between FPGA devices and DSP devices. This metric estimates the quality of implementations based on the efficiency of resources utilization in both technologies. A case study of a magnitude and phase angle detector of the fundamental-frequency positive-sequence component of a three-phase signal is presented. As a second contribution, a proposed FPGA-controller architecture is presented. For validation of the proposed metric, the advantages and possibilities of the use of FPGA in the case study are demonstrated in comparison with the DSP, in terms of the efficiency of resource usage metric, which is based on the capacity for increasing the application algorithms complexity and capacity of exploring the parallelism of operations, allowing for a much shorter execution time.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132655907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Top-down design for Low power Multi-bit Sigma-Delta Modulator 低功耗多比特Sigma-Delta调制器的自顶向下设计

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344448

H. Cubas, J. Soares

引用次数: 2

Communication software synthesis from UML-ESL models 从UML-ESL模型合成通信软件

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344449

Thiago N. C. Cardoso, E. Barros, B. Prado, Andre Aziz

{"title":"Communication software synthesis from UML-ESL models","authors":"Thiago N. C. Cardoso, E. Barros, B. Prado, Andre Aziz","doi":"10.1109/SBCCI.2012.6344449","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344449","url":null,"abstract":"The electronic devices market demands a larger amount of functionality integrated into a single product. To address this demand, the industry migrated to solutions based on processors, increasing the software role in the systems. However, processor-based solutions raises the design complexity due to the complexity of Hardware-dependent Software (HdS). To cope with this complexity, the virtual platforms approach is applied, in which the whole system is modeled in order to reduce the design time. Nowadays, much of this work is manually performed, synthesizing all structures and behavior required in a system level design language (SLDL). However, with the increasing systems complexity, it is becoming impractical to continue performing this synthesis manually. In the last decade, several studies have addressed the synthesis of software components from descriptions in SLDLs and recently in the Unified Modeling Language (UML). Although significant automation has been obtained, there are limitations in the abstraction achieved. In order to raise the abstraction of the description, the UML-ESL profile was proposed to abstract the communication structure, with a synthesis technique for communication between software and hardware interfaces. This work presents a technique to synthesize the multitasking support and the communication between software components of the system from a description in UML-ESL for virtual platform simulation. The results obtained showed up to 60% decrease in the amount of code manually written.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128872791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Kernel analysis for architecture design trade off in convolution-based image filtering 基于卷积的图像滤波中结构设计权衡的核分析

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344453

J. Y. Mori, C. Llanos, P. Berger

引用次数: 14

Design-oriented delay model for CMOS inverter 面向设计的CMOS逆变器延迟模型

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344424

F. Marranghello, A. Reis, R. Ribas

引用次数: 5

Hybrid-on-chip communication architecture for dynamic MP-SoC protection 用于动态MP-SoC保护的片上混合通信架构

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344419

Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum

{"title":"Hybrid-on-chip communication architecture for dynamic MP-SoC protection","authors":"Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum","doi":"10.1109/SBCCI.2012.6344419","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344419","url":null,"abstract":"MPSoCs are able to support multiple applications on the same chip. This flexibility also represents a vulnerability, turning the MPSoC security specially challenging. Most of the current MPSoCs security services are based on symmetric and public-key cryptographic mechanisms. So that, MPSoCs integrate a large set of keys that must be exchanged in an efficient and secure way. In such scenario, any security concept will be ineffective if the key management is weak. In this paper, we present the implementation of an on-chip hybrid communication (HoCs) security-based architecture, that combines bus and Network-on-chip (NoC), to address the efficient and secure key management at MPSoCs. The HoC implements dynamically the QoSS (Quality of Security Service) concept that allows the customization of security. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications. Our hybrid approach saves upto 16% and 25% of communication latency and power consumption, respectively, when compared to the NoC-based architecture without any security.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"87 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124734477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Heterogeneous system-level modeling for small and medium enterprises 中小型企业的异构系统级建模

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344450

Seyed-Hosein Attarzadeh-Niaki, Gilmar S. Beserra, N. Andersen, Mathias Verdon, I. Sander

引用次数: 4

Multi-bit flip-flop usage impact on physical synthesis 多比特触发器使用对物理合成的影响

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2012-11-12 DOI: 10.1109/SBCCI.2012.6344435

C. Santos, R. Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte

{"title":"Multi-bit flip-flop usage impact on physical synthesis","authors":"C. Santos, R. Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte","doi":"10.1109/SBCCI.2012.6344435","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344435","url":null,"abstract":"Reducing clock network power is an efficient way to reduce power consumption of the high-frequency ASICs since it accounts for a considerable amount of the dynamic chip power. Recently, the use of multi-bit flip-flops (MBFFs) has been shown to be an effective design technique to improve clock tree synthesis and can be used either as an alternative or in conjunction with the well-known clock gating approach targeting clock power reduction. The idea behind this technique is that clock tree power savings can be achieved by using flip-flop cells with optimized design and also through a reduced clock tree once the number of clock sinks is smaller in a design with MBFF cells. Some recent works have been proposing methods to take advantage of using MBFFs in standard cell based designs, where single-bit flip-flops are replaced by MBFF cells during logic and/or physical syntheses. However, a more complete analysis is still needed for different steps of a design flow to help understanding the impact of MBFFs on the physical design. We present in this work a comprehensive comparison between traditional flip-flop and MBFF implementations of an industrial 55nm design. Our results consider area, power and timing as well as some side effects like clock skew, routing congestion and voltage drop distribution. Finally, this study points to some potential drawbacks of using MBFFs which may be helpful for designers to make trade-off decisions in high performance SoC designs.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130674272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14