2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems"最新文献_第6页

MIXDES 2019 Author Index MIXDES 2019作者索引

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/mixdes.2019.8787115

引用次数: 0

Area Efficient High-voltage Charge Pump for Double Backplate MEMS Microphone 双背板MEMS麦克风区域高效高压充电泵

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787044

L. Zou, Tomasz Hanzlik, Gino Rocca

{"title":"Area Efficient High-voltage Charge Pump for Double Backplate MEMS Microphone","authors":"L. Zou, Tomasz Hanzlik, Gino Rocca","doi":"10.23919/MIXDES.2019.8787044","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787044","url":null,"abstract":"Silicon MEMS microphones show competitive advantages to portable consumer electronics with tiny device size, high sound quality, reliability and affordability. The application of MEMS analog/digital microphones can now be found in smart phones, hearing aids, tablets, and automotive voice recognition systems. A double backplate (DB) MEMS transducer brings higher sensitivity and lower distortion compared to a single backplate MEMS. In this paper, we first show an attractive DB MEMS analog microphone where two sufficiently high positive DC voltages are required to bias top and bottom backplates, respectively. As a solution, a fully integrated dual-output high-voltage (HV) positive charge pump is proposed, and the layout area saving is about 40%. To verify the design, an analog readout ASIC is fabricated in a standard 0.18 um CMOS process, and the ASIC includes the proposed HV charge pump, clock generation, and other circuit blocks. In silicon validation, two voltages 12.42 V and 12.40 V with no ripples are generated successfully, and the settling time is well within 5 mS. The two voltages can be perfectly applied to the DB MEMS.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121737604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Minimization of SM-Covers of Petri Net Specifications of Control Systems 控制系统Petri网规格sm -盖的最小化

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787097

A. Karatkevich, Lukasz Stefanowicz

引用次数: 0

A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology 65纳米CMOS技术的高分辨率、宽范围、抗辐射时钟移相器

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787202

S. Kulis, Dong-xu Yang, Datao Ghong, J. Fonseca, S. Biereigel, J. Ye, P. Moreira

引用次数: 1

A 130 nm CMOS Passive Mixer Utilizing Positive-Negative Feedback as the Input Transconductance 利用正负反馈作为输入跨导的130 nm CMOS无源混频器

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787186

A. Zokaei, K. El-Sankary, Dmitry Trukhachev, A. Amirabadi

引用次数: 0

A Simple Ultra-Low Power Opamp in 22 nm FDSOI 一种简单的22纳米FDSOI超低功耗运放

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787017

W. Kuzmicz

引用次数: 4

Implementation of Addition and Subtraction Operations in Multiple Precision Arithmetic 多重精度算术中加减运算的实现

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787156

K. Rudnicki, T. Stefański

{"title":"Implementation of Addition and Subtraction Operations in Multiple Precision Arithmetic","authors":"K. Rudnicki, T. Stefański","doi":"10.23919/MIXDES.2019.8787156","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787156","url":null,"abstract":"In this paper, we present a digital circuit of arithmetic unit implementing addition and subtraction operations in multiple-precision arithmetic (MPA). This adder-subtractor unit is a part of MPA coprocessor supporting and offloading the central processing unit (CPU) in computations requiring precision higher than 32/64 bits. Although addition and subtraction operations of two n-digit numbers require O(n) operations, the efficient implementation of these operations can provide valuable time-savings for the MPA coprocessor. Furthermore, MPA numbers are usually stored with the use of the sign-magnitude representation which is not so straightforward for addition/subtraction implementation as the two’s complement representation.Our adder-subtractor unit is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. The developed digital circuit of the MPA adder-subtractor works with integer numbers of precision varying in the range between 64 bits and 32 kbits with the limb size set to 64 bits. It can currently work with the clock frequency exceeding 450 MHz. For the developed implementation, the addition of two k-limb numbers takes 33+k clock cycles. Hence, the developed coprocessor is 1.7 times faster than a single core of modern i7 processor for precision set to 32704 bits.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD) 带复合鉴相器(CPD)的快锁、低抖动、高速半速率CDR架构

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787120

Zaher Kakehbra, Morteza Mousazadeh, A. Khoei, A. Dadashi

{"title":"A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD)","authors":"Zaher Kakehbra, Morteza Mousazadeh, A. Khoei, A. Dadashi","doi":"10.23919/MIXDES.2019.8787120","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787120","url":null,"abstract":"A half-rate CDR architecture is presented which exploits an improved half-rate Linear Phase Detector (LPD) and a proposed half-rate Multi-Level Bang Bang PD (MLBBPD) incorporated in a Composite PD (CPD) to benefit the advantages of both the MLBBPD and LPD such as fast locking and good jitter performance, respectively. The proposed half-rate LPD in contrast with a conventional counterpart generates the error and reference signals with the equivalent pulse width, thus obviating to employ asymmetric charge pump, also relaxes the speed requirement of other related circuits. Finally, its systematic phase offset is zero. During lock acquisition, the MLBBPD controls the CDR loop due to fast lock time. At locked state, the LPD establishes the loop owing to better jitter operation. Switching between the MLBBPD and LPD is performed through a proposed Lock Detector (LD). At the locked state, if the phase difference between the data and the clock be greater than 45, the LD selects the MLBBPD to decrease it below 45, and again the LPD is selected. Simulations accomplished by Verilog-AMS model in HSPICE-RF simulator and the results confirm our statements.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123851743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of SiC MOSFET Electrical Model and Experimental Validation: Improvement and Reduction of Parameter Number SiC MOSFET电学模型的建立与实验验证:参数数的改进与减少

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787050

Quang Chuc Nguyen, P. Tounsi, J. Fradin, J. Reynes

引用次数: 0

Low Power Design From Moore to AI for nm Era : Invited Paper 纳米时代从摩尔到人工智能的低功耗设计:特邀论文

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI: 10.23919/MIXDES.2019.8787172

R. Joshi, M. Ziegler

引用次数: 0