A. Hefner, D. Berning, D. Blackburn, C. Chapuy, S. Bouche
{"title":"A high-speed thermal imaging system for semiconductor device analysis","authors":"A. Hefner, D. Berning, D. Blackburn, C. Chapuy, S. Bouche","doi":"10.1109/STHERM.2001.915143","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915143","url":null,"abstract":"A new high-speed transient thermal imaging system is presented that provides the capability to measure the transient temperature distributions on the surface of a semiconductor chip with 1 /spl mu/s time, and 15 /spl mu/m spatial resolution. The system uses virtual instrument graphical user interface software that controls an infrared thermal microscope, translation stages, a digitizing oscilloscope, and a device test fixture temperature controller. The computer interface consists of a front panel for viewing the temperature distribution and includes a movie play-back feature that enables viewing of the temperature distribution versus time. The computer user interface also has a sub-panel for emissivity mapping and calibration of the infrared detector. The utility of the system is demonstrated in this paper using a bipolar transistor hotspot current constriction process.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tool for fast modelling active heat sinks","authors":"P. Dziurdzia, A. Kos","doi":"10.1109/STHERM.2001.915175","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915175","url":null,"abstract":"The paper presents a tool for electrothermal simulation and very fast modelling of active heat sinks. The tool is based on a special electrothermal model of an active heat sink and makes use of the SPICE electronic circuit simulator. By this means, one can find values of electric current supplying a thermo-electric device in order to change the temperature of a cooled object according to a given algorithm. The electrothermal model of an active heat sink, a method of calculating control functions of a Peltier device supplying electric current, and examples of simulations are shown.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125253928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal management for high performance integrated circuits with non-uniform chip power considerations","authors":"T. Yuan, B. Z. Hong, H.H. Chen, Li-Kong Wang","doi":"10.1109/STHERM.2001.915154","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915154","url":null,"abstract":"Thermal management for nonuniform chip power integrated circuits is studied. Circuit chip power analysis was used to generate nonuniform chip power and computational fluid dynamics (CFD) techniques are used to calculate the chip temperature. This paper also presents an integrated thermomechanical analysis of a ceramic ball grid array (CBGA) single chip module (SCM) system under chip power loads. A three-dimensional finite element model (FEM) was used for the sequential heat transfer and mechanical analyses to predict the temperature gradients and associated structural response of stress and deformation of the SCM. The thermomechanical analysis results are used to examine the integral effect of chip power loading conditions and of two design parameters, the substrate and cap materials, on the structural integrity of the modeled CBGA SCM system.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130887351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal design of a desktop computer system using CFD analysis","authors":"C. Yu, R. Webb","doi":"10.1109/STHERM.2001.915139","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915139","url":null,"abstract":"This paper uses CFD (Icepak) to identify a cooling solution for a desktop computer, which uses an 80 W CPU. The design is based on a total chassis power dissipation of 313 W (40 W PCI cards). This represents significant power dissipation for the chassis components (memory, chipset, AGP and PCI cards, and peripherals). The analysis is also extended to 100 W PCI power. Of key interest is minimization of the chassis air flow requirements. The design is able to cool the chassis with one case fan and the power supply fan. A ducted 80/spl times/60 mm CPU heat sink is able to meet the CPU temperature specification. System level design improvements were made to provide better cooling for AGP and PCI cards.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127601477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Temperature sensors placement strategy for fault diagnosis in integrated circuits","authors":"P. Bratek, A. Kos","doi":"10.1109/STHERM.2001.915185","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915185","url":null,"abstract":"In this paper, we present a new temperature sensor placement strategy. This placement method is proposed for fault diagnosis in integrated circuits (ICs). Simulation results of the new concept sensor placement strategy are presented. Statistical analyses of the yield of this testing method are shown.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134574147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Current and future miniature refrigeration cooling technologies for high power microelectronics","authors":"Patrick E. Phelan, V. Chiriac, T. Lee","doi":"10.1109/STHERM.2001.915172","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915172","url":null,"abstract":"Utilizing refrigeration may provide the only means by which future high-performance electronic chips can be maintained below predicted maximum temperature limits. Widespread application of refrigeration in electronic packaging will remain limited until the refrigerators can be made sufficiently small so that they can be easily incorporated within the packaging. A review of existing microscale and mesoscale refrigeration systems revealed that only thermoelectric coolers (TECs) are now commercially available in small sizes. However, existing TECs are limited by their maximum cooling power and low efficiencies. A simple model was constructed to analyze the performance of both existing and predicted future TECs in an electronic packaging environment. Comparison with the cooling provided by an existing high-performance fan shows that they are most effective for heat loads less than approximately 100 W, but that for higher heat loads, fan air cooling actually yields a lower junction temperature. If the efficiency of future TECs, as characterized by ZT/sub room/, where Z is the figure of merit and T/sub room/ is room temperature, can be increased from the present value of /spl sim/0.8 to 2 or even 3, TEC performance improves dramatically, thus making them competitive for many electronic applications. Finally, one unanticipated result of the model was the realization that the thermal resistance between the refrigerator and the chip is not as critical as the thermal resistance between the refrigerator and the ambient air.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129603497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effect of flag design on thermal performance of PBGA packages","authors":"B. Joiner","doi":"10.1109/STHERM.2001.915182","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915182","url":null,"abstract":"In order to meet performance requirements, the package design of the 272 27/spl times/27 mm PBGA package must incorporate the best possible thermal path from the die to the printed circuit board to which the package is attached. Unfortunately, the reliability requirements for passing moisture resistance are more easily passed with a minimum amount of copper under the die. This paper reports finite element thermal simulations predicting the effect of the design options on thermal performance. Switching from a solid flag with a solid spreader pad on the bottom of the substrate to a minimal copper design would cause about 3 to 6/spl deg/C/watt increase in junction temperature.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124817270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic electro-thermal physically based compact models of the power devices for device and circuit simulations","authors":"P. Igić, P. Mawby, M. Towers, S. Batcup","doi":"10.1109/STHERM.2001.915142","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915142","url":null,"abstract":"New dynamic electro-thermal models of the power MOSFET, and power bipolar devices (PiN diode and IGBT) are presented in this paper. Firstly, electric device models were made, and then they were transformed into the electro-thermal models by adding a thermal node. This thermal node stores information about junction temperature and represents a connection between the device and rest of the circuit thermal network. All models have been found to be efficient and robust in all cases examined.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wiring statistics and printed wiring board thermal conductivity","authors":"R. D. Nelson","doi":"10.1109/STHERM.2001.915186","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915186","url":null,"abstract":"The thermal conductivity of printed wiring boards depends strongly upon the copper content of the signal and power planes. For boards with continuous power and ground planes, it is adequate to use simple lumped conductivities based on the volume percentage of copper. However, nearly order of magnitude errors can occur when this approach is used with boards with discontinuous or significantly perforated power and ground planes. We describe a statistical approach to modeling the copper connectivity in wired signal planes, based on the probability distribution of wire lengths in the X and Y directions. Using this approach, we have constructed finite element models of six-layer printed wiring boards which approximate functional boards with a wide range of wiring density, via density, and power/ground plane perforations. The finite element results show that the connectivity of the wiring, vias, and power/ground planes plays an important role in establishing the board's average thermal conductivity. Although there is some scatter in the results, due to wiring details, we find that the percentage of copper in the printed wiring board can still be used as an initial indicator of thermal conductivity. We present an empirical fit to the models suitable for design applications.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129386359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Chien, Ming-Hsi Tseng, Chih-Yao Wang, Chu Chun-Hsun
{"title":"The study of micro-fin heat sinks for electronic cooling applications","authors":"H. Chien, Ming-Hsi Tseng, Chih-Yao Wang, Chu Chun-Hsun","doi":"10.1109/STHERM.2001.915181","DOIUrl":"https://doi.org/10.1109/STHERM.2001.915181","url":null,"abstract":"A variety of pin fin parameters were studied and tested to calculate an empirical relationship which can predict the optimum thermal performance of the micro pin fin structure. The sample parameters tested are as follows: (1) fin size from 0.2 mm to 1.0 mm; (2) fin height from 2.0 mm to 10.0 mm. The errors from comparison of the empirical relationship with the test data are less than 5%, so we can use this empirical relationship to estimate the optimum performance of pin fin heat sinks. According to the results from empirical relationship, the ratio of optimum fin pitch to fin size (fin pitch/fin size) is about 1.5/spl sim/1.7. Greater fin height gives higher thermal performance, and a smaller fin size structure has the potential for better thermal performance than huge fin size structures.","PeriodicalId":307079,"journal":{"name":"Seventeenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.01CH37189)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120953616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}